[v5,09/27] irqchip/gic: Lower priority of GIC interrupts

Message ID	1535471497-38854-10-git-send-email-julien.thierry@arm.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org> From: Julien Thierry <julien.thierry@arm.com> To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 09/27] irqchip/gic: Lower priority of GIC interrupts Date: Tue, 28 Aug 2018 16:51:19 +0100 Message-Id: <1535471497-38854-10-git-send-email-julien.thierry@arm.com> In-Reply-To: <1535471497-38854-1-git-send-email-julien.thierry@arm.com> References: <1535471497-38854-1-git-send-email-julien.thierry@arm.com> Precedence: list Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, Julien Thierry <julien.thierry@arm.com>, marc.zyngier@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, christoffer.dall@arm.com, james.morse@arm.com, joel@joelfernandes.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org
Series	arm64: provide pseudo NMI with GICv3 \| expand [v5,00/27] arm64: provide pseudo NMI with GICv3 [v5,01/27] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature [v5,02/27] arm64: cpufeature: Use alternatives for VHE cpu_enable [v5,03/27] arm64: alternative: Apply alternatives early in boot process [v5,04/27] arm64: daifflags: Use irqflags functions for daifflags [v5,05/27] arm64: Use daifflag_restore after bp_hardening [v5,06/27] arm64: Delay daif masking for user return [v5,07/27] arm64: xen: Use existing helper to check interrupt status [v5,08/27] irqchip/gic: Unify GIC priority definitions [v5,09/27] irqchip/gic: Lower priority of GIC interrupts [v5,10/27] arm64: cpufeature: Add cpufeature for IRQ priority masking [v5,11/27] arm64: Make PMR part of task context [v5,12/27] arm64: Unmask PMR before going idle [v5,13/27] arm/arm64: gic-v3: Add helper functions to manage IRQ priorities [v5,14/27] arm64: kvm: Unmask PMR before entering guest [v5,15/27] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking [v5,16/27] arm64: daifflags: Include PMR in daifflags restore operations [v5,17/27] irqchip/gic-v3: Factor group0 detection into functions [v5,18/27] irqchip/gic-v3: Do not overwrite PMR value [v5,19/27] irqchip/gic-v3: Remove acknowledge loop [v5,20/27] irqchip/gic-v3: Switch to PMR masking after IRQ acknowledge [v5,21/27] arm64: Switch to PMR masking when starting CPUs [v5,22/27] arm64: Add build option for IRQ masking via priority [v5,23/27] arm64: Handle serror in NMI context [v5,24/27] irqchip/gic-v3: Detect current view of GIC priorities [v5,25/27] irqchip/gic-v3: Add base support for pseudo-NMI [v5,26/27] irqchip/gic: Add functions to access irq priorities [v5,27/27] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI

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1535471497-38854-10-git-send-email-julien.thierry@arm.com (mailing list archive)

State

New, archived

Headers

From: Julien Thierry <julien.thierry@arm.com>
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 09/27] irqchip/gic: Lower priority of GIC interrupts
Date: Tue, 28 Aug 2018 16:51:19 +0100
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 Julien Thierry <julien.thierry@arm.com>, marc.zyngier@arm.com,
 catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org,
 christoffer.dall@arm.com, james.morse@arm.com, joel@joelfernandes.org
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Series

arm64: provide pseudo NMI with GICv3 | expand

Commit Message

Julien Thierry Aug. 28, 2018, 3:51 p.m. UTC

The current value used for IRQ priorities is high among the
non-secure interrupt priority values.

Lower the default priority of interrupts so there is more flexibility
to define higher priority interrupts.

Tested-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Suggested-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
---
 include/linux/irqchip/arm-gic-common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--
1.9.1

diff --git a/include/linux/irqchip/arm-gic-common.h b/include/linux/irqchip/arm-gic-common.h
index 9a1a479..2c9a4b3 100644
--- a/include/linux/irqchip/arm-gic-common.h
+++ b/include/linux/irqchip/arm-gic-common.h
@@ -13,7 +13,7 @@ 
 #include <linux/types.h>
 #include <linux/ioport.h>

-#define GICD_INT_DEF_PRI		0xa0
+#define GICD_INT_DEF_PRI		0xc0
 #define GICD_INT_DEF_PRI_X4		((GICD_INT_DEF_PRI << 24) |\
 					(GICD_INT_DEF_PRI << 16) |\
 					(GICD_INT_DEF_PRI << 8) |\

[v5,09/27] irqchip/gic: Lower priority of GIC interrupts

Commit Message

Patch