| Message ID | 1539155912-29760-3-git-send-email-wendy.liang@xilinx.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Xilinx ZynqMP IPI Mailbox Controller Driver | expand |
On Wed, Oct 10, 2018 at 12:18:32AM -0700, Wendy Liang wrote: > Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block > in ZynqMP SoC used for the communication between various processor > systems. > > Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> [...] > +Optional properties: > +-------------------- > +- method: The method of accessing the IPI agent registers. > + Permitted values are: "smc" and "hvc". Default is > + "smc". You are mixing the hardware messaging based mailbox and the software "smc/hvc" based mailbox together here. Please keep them separated. IIUC smc/hvc based mailcox is used for "tx" or too keep it simple in one direction and hardware based is used for "rx" or the other direction for communication. You *should not* mix them as single unit. Also lots of other vendor need SMC/HVC based mailbox. So make it generic and keep it separate. -- Regards, Sudeep
On Wed, Oct 10, 2018 at 2:59 AM Sudeep Holla <sudeep.holla@arm.com> wrote: > > On Wed, Oct 10, 2018 at 12:18:32AM -0700, Wendy Liang wrote: > > Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block > > in ZynqMP SoC used for the communication between various processor > > systems. > > > > Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> > > [...] > > > +Optional properties: > > +-------------------- > > +- method: The method of accessing the IPI agent registers. > > + Permitted values are: "smc" and "hvc". Default is > > + "smc". > > You are mixing the hardware messaging based mailbox and the software > "smc/hvc" based mailbox together here. Please keep them separated. > IIUC smc/hvc based mailcox is used for "tx" or too keep it simple in > one direction and hardware based is used for "rx" or the other direction > for communication. > Hi Sudeep, Thanks for your comments. The IPI hardware block has both buffers and registers. The hardware block has dedicated buffers for each mailboxes, and thus, in the implementation, we directly access the buffers from IPI driver. However, the controller registers are shared between mailboxes in the hardware, as the ATF will also access the registers, we need to use SMC/HVC to access the registers (control or ISR). And the SMC/HVC here is for the register access. I am not clear on smc/hvc based mailbox is used for tx, and hardware based is used for "rx". As for both TX and RX, we need to write/read the registers (through SMC) and write/read the buffers provided by the IPI hardware block directly. Thanks, Wendy > You *should not* mix them as single unit. Also lots of other vendor need > SMC/HVC based mailbox. So make it generic and keep it separate. > > -- > Regards, > Sudeep
> -----Original Message----- > From: Wendy Liang [mailto:sunnyliangjy@gmail.com] > Sent: Wednesday, October 10, 2018 3:54 PM > To: Sudeep Holla <sudeep.holla@arm.com> > Cc: Jiaying Liang <jliang@xilinx.com>; Jassi Brar <jassisinghbrar@gmail.com>; > Michal Simek <michals@xilinx.com>; Rob Herring <robh+dt@kernel.org>; > Mark Rutland <mark.rutland@arm.com>; Devicetree List > <devicetree@vger.kernel.org>; Linux Kernel Mailing List <linux- > kernel@vger.kernel.org>; linux-arm-kernel <linux-arm- > kernel@lists.infradead.org> > Subject: Re: [PATCH v4 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox > > On Wed, Oct 10, 2018 at 2:59 AM Sudeep Holla <sudeep.holla@arm.com> > wrote: > > > > On Wed, Oct 10, 2018 at 12:18:32AM -0700, Wendy Liang wrote: > > > Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block in > > > ZynqMP SoC used for the communication between various processor > > > systems. > > > > > > Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> > > > > [...] > > > > > +Optional properties: > > > +-------------------- > > > +- method: The method of accessing the IPI agent registers. > > > + Permitted values are: "smc" and "hvc". Default is > > > + "smc". > > > > You are mixing the hardware messaging based mailbox and the software > > "smc/hvc" based mailbox together here. Please keep them separated. > > IIUC smc/hvc based mailcox is used for "tx" or too keep it simple in > > one direction and hardware based is used for "rx" or the other > > direction for communication. > > > Hi Sudeep, > > Thanks for your comments. > > The IPI hardware block has both buffers and registers. The hardware block > has dedicated buffers for each mailboxes, and thus, in the implementation, > we directly access the buffers from IPI driver. However, the controller > registers are shared between mailboxes in the hardware, as the ATF will also > access the registers, we need to use SMC/HVC to access the registers (control > or ISR). And the SMC/HVC here is for the register access. > > I am not clear on smc/hvc based mailbox is used for tx, and hardware based > is used for "rx". As for both TX and RX, we need to write/read the registers > (through SMC) and write/read the buffers provided by the IPI hardware block > directly. [Wendy] Hi Sudeep, The SMC/HVC is for hardware registers access as but not sending messages. Do you have further comments or are you fine with the explanation? Thanks, Wendy > > Thanks, > Wendy > > > You *should not* mix them as single unit. Also lots of other vendor > > need SMC/HVC based mailbox. So make it generic and keep it separate. > > > > -- > > Regards, > > Sudeep
diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt new file mode 100644 index 0000000..146f2fb --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt @@ -0,0 +1,128 @@ +Xilinx IPI Mailbox Controller +======================================== + +The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage +messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI +agent owns registers used for notification and buffers for message. + + +-------------------------------------+ + | Xilinx ZynqMP IPI Controller | + +-------------------------------------+ + +--------------------------------------------------+ +ATF | | + | | + | | + +--------------------------+ | + | | + | | + +--------------------------------------------------+ + +------------------------------------------+ + | +----------------+ +----------------+ | +Hardware | | IPI Agent | | IPI Buffers | | + | | Registers | | | | + | | | | | | + | +----------------+ +----------------+ | + | | + | Xilinx IPI Agent Block | + +------------------------------------------+ + + +Controller Device Node: +=========================== +Required properties: +-------------------- +IPI agent node: +- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox" +- interrupt-parent: Phandle for the interrupt controller +- interrupts: Interrupt information corresponding to the + interrupt-names property. +- xlnx,ipi-id: local Xilinx IPI agent ID +- #address-cells: number of address cells of internal IPI mailbox nodes +- #size-cells: number of size cells of internal IPI mailbox nodes + +Internal IPI mailbox node: +- reg: IPI buffers address ranges +- reg-names: Names of the reg resources. It should have: + * local_request_region + - IPI request msg buffer written by local and read + by remote + * local_response_region + - IPI response msg buffer written by local and read + by remote + * remote_request_region + - IPI request msg buffer written by remote and read + by local + * remote_response_region + - IPI response msg buffer written by remote and read + by local +- #mbox-cells: Shall be 1. It contains: + * tx(0) or rx(1) channel +- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is + connected to. + +Optional properties: +-------------------- +- method: The method of accessing the IPI agent registers. + Permitted values are: "smc" and "hvc". Default is + "smc". + +Client Device Node: +=========================== +Required properties: +-------------------- +- mboxes: Standard property to specify a mailbox + (See ./mailbox.txt) +- mbox-names: List of identifier strings for each mailbox + channel. + +Example: +=========================== + zynqmp_ipi { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0 29 4>; + xlnx,ipi-id = <0>; + #address-cells = <1>; + #size-cells = <1>; + + /* APU<->RPU0 IPI mailbox controller */ + ipi_mailbox_rpu0: mailbox@ff90400 { + compatible = "xlnx,zynqmp-ipi-mailbox"; + reg = <0xff990400 0x20>, + <0xff990420 0x20>, + <0xff990080 0x20>, + <0xff9900a0 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <1>; + xlnx-ipi-id = <1>; + }; + /* APU<->RPU1 IPI mailbox controller */ + ipi_mailbox_rpu1: mailbox@ff990440 { + compatible = "xlnx,zynqmp-ipi-mailbox"; + reg = <0xff990440 0x20>, + <0xff990460 0x20>, + <0xff990280 0x20>, + <0xff9902a0 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <1>; + xlnx-ipi-ids = <2>; + }; + }; + rpu0 { + ... + mboxes = <&ipi_mailbox_rpu0 0>, + <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; + rpu1 { + ... + mboxes = <&ipi_mailbox_rpu1 0>, + <&ipi_mailbox_rpu1 1>; + mbox-names = "tx", "rx"; + };
Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block in ZynqMP SoC used for the communication between various processor systems. Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> --- Not put "Reviewed-by" as bindings have been updated since last review. --- .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 128 +++++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt