clk: imx7d: remove UART1 clock setting

Commit Message

Anson Huang Oct. 18, 2018, 6:51 a.m. UTC

There is clock assignment in dtb for UART1, so setting
UART1 clock in clock driver is NOT necessary.

Signed-off-by: Anson Huang <[e-mail]>
---
 drivers/clk/imx/clk-imx7d.c | 3 ---
 1 file changed, 3 deletions(-)

Comments

Stephen Boyd Oct. 18, 2018, 6:01 p.m. UTC | #1

Quoting Anson Huang (2018-10-17 23:51:55)
> There is clock assignment in dtb for UART1, so setting
> UART1 clock in clock driver is NOT necessary.

Can you mention the commit that introduced the assignment and possibly
the file where it is done?

> 
> Signed-off-by: Anson Huang <[e-mail]>

Patch

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index adb08f6..06c105d 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -886,9 +886,6 @@  static void __init imx7d_clocks_init(struct device_node *ccm_node)
 	/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
 	clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
 
-	/* set uart module clock's parent clock source that must be great then 80MHz */
-	clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
-
 	/* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */
 	clks[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
 	clks[IMX7D_USB_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb_main_clk", "osc", 20, 1);