diff mbox series

[V2] clk: imx7d: remove UART1 clock setting

Message ID 1539910863-2352-1-git-send-email-Anson.Huang@nxp.com (mailing list archive)
State New, archived
Headers show
Series [V2] clk: imx7d: remove UART1 clock setting | expand

Commit Message

Anson Huang Oct. 19, 2018, 1:05 a.m. UTC
There are clock assignments in all i.MX7D dtb files for UART1,
below is the example in imx7d-sdb.dts, so setting UART1 clock
in clock driver is NOT necessary, actually, module clocks setting
should be done in module driver.

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	status = "okay";
};

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
 drivers/clk/imx/clk-imx7d.c | 3 ---
 1 file changed, 3 deletions(-)

Comments

Stephen Boyd Nov. 6, 2018, 5:35 p.m. UTC | #1
Quoting Anson Huang (2018-10-18 18:05:36)
> There are clock assignments in all i.MX7D dtb files for UART1,
> below is the example in imx7d-sdb.dts, so setting UART1 clock
> in clock driver is NOT necessary, actually, module clocks setting
> should be done in module driver.
> 
> &uart1 {
>         pinctrl-names = "default";
>         pinctrl-0 = <&pinctrl_uart1>;
>         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
>         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
>         status = "okay";
> };
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---

Applied to clk-next
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index adb08f6..06c105d 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -886,9 +886,6 @@  static void __init imx7d_clocks_init(struct device_node *ccm_node)
 	/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
 	clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
 
-	/* set uart module clock's parent clock source that must be great then 80MHz */
-	clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
-
 	/* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */
 	clks[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
 	clks[IMX7D_USB_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb_main_clk", "osc", 20, 1);