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Miller" , sparclinux@vger.kernel.org, Michael Ellerman Subject: [PATCH v2 12/20] mips: perf/core: advertise PMU exclusion capability Date: Mon, 26 Nov 2018 11:12:28 +0000 Message-Id: <1543230756-15319-13-git-send-email-andrew.murray@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543230756-15319-1-git-send-email-andrew.murray@arm.com> References: <1543230756-15319-1-git-send-email-andrew.murray@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181126_111425_401198_3B3DD6B0 X-CRM114-Status: GOOD ( 11.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-s390@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The MIPS PMU has the capability to exclude events based on context. Let's advertise that we support the PERF_PMU_CAP_EXCLUDE capability to ensure that perf doesn't prevent us from handling events where any exclusion flags are set. Signed-off-by: Andrew Murray --- arch/mips/kernel/perf_event_mipsxx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 4138635..d7813d0 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -670,6 +670,7 @@ static struct pmu pmu = { .start = mipspmu_start, .stop = mipspmu_stop, .read = mipspmu_read, + .capabilities = PERF_PMU_CAP_EXCLUDE, }; static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)