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bh=2FtMUMqjTWgq7+H0Xzq37jlZmPw4eMxM5z6ejmBhAUg=; b=s+OhqrpkFg10um2aZxCvsyRCH4pe0tQn+OalsajipxckbjYj46CZdy2eCHBCNs2eL0 ltmmOuYMF7R8TvrIGuPSn2moC4EjINqidOhuXLUYqRV2fnTkSrpLaZ72FPDq1vdsGbnL 1inhyv/zIjcS+xePVd965iGDo9/32aW9hAmr3CTZSy9G2d05qRMY1ZuVVfB7T41Vp59j /Prl+fWrb3PMmntWL+Qf2Kx6C+079aYw5MwPew8A3l8o+WRxIWfeJ8KVSMv6s9lmK970 3mQCRqIJvLVY3itmvRXdfsOcPqdZ3xGNa80mOCiv4sWm/3eorfpkstiIn/gv2kwYiTtz LzbA== X-Gm-Message-State: AA+aEWbIh0SBmyDXYh9A5LrSpXzCzvA0XKJKVcPKAzkaGk2T4wnDntOF il+CcPsQr0/irV+50Jo2sM8= X-Google-Smtp-Source: AFSGD/XjF+bItbIc9cH+dcleM8oxzN2Hd06lCzddQ6XS4qGWMvVp9PHZg3ai/o1+IKZUQRvq8wk8zA== X-Received: by 2002:a37:268b:: with SMTP id m11mr25969809qkm.131.1543257963933; Mon, 26 Nov 2018 10:46:03 -0800 (PST) Received: from localhost.localdomain ([201.82.144.36]) by smtp.gmail.com with ESMTPSA id i33sm427489qtb.97.2018.11.26.10.46.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Nov 2018 10:46:03 -0800 (PST) From: Fabio Estevam To: shawnguo@kernel.org Subject: [RFC 1/2] ARM: dts: imx6ul: Correct mask for GIC PPI interrupts Date: Mon, 26 Nov 2018 16:45:54 -0200 Message-Id: <1543257955-8910-1-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181126_104615_604356_2C1B9798 X-CRM114-Status: GOOD ( 14.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, liviu.dudau@arm.com, linux-imx@nxp.com, kernel@pengutronix.de, Fabio Estevam , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual number of CPU cores the interrupt controller is wired to. i.MX6UL contains a single Cortex-A7, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)". Tested on a imx6ul-evk. Signed-off-by: Fabio Estevam --- Hi, This is based on the following commit: commit 2acb79e15119512da9b6a49906840e7678cfb618 Author: Geert Uytterhoeven Date: Mon May 7 15:19:52 2018 +0200 ARM: dts: r8a7790: Correct mask for GIC PPI interrupts R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts can be delivered to all 8 processor cores. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman and the confirmation from Liviu Dudau that GIC_CPU_MASK_SIMPLE() should take the number of cores in the system as the argument: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315298.html arch/arm/boot/dts/imx6ul.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index c71d2d6..b8f5ef2 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -108,10 +108,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-parent = <&intc>; status = "disabled"; };