From patchwork Thu Nov 29 23:28:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 10705535 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB8F813A4 for ; Thu, 29 Nov 2018 23:29:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DA76B2FAEE for ; Thu, 29 Nov 2018 23:29:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CE5D62FAFD; Thu, 29 Nov 2018 23:29:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 44FB22FAEE for ; Thu, 29 Nov 2018 23:29:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=mRfXy13Ty/vp+VptoVcnurrS9Lc0AK5qUFt/+UFfW84=; b=PU0ctuNCC8Ny90uy4aiTOjzLgL 1sbWGo7uloIpFVCB5EmwcA1938MGfE6Yd0mOokERiqGxtOUIoUtSFtHAhv8Yz/kdzwIypXnsfr8AR +qUOrtRp3SbGDtuin8RwfjPGaanrNuPVEJmZUp3U7pH9DjYyE1xAk56hMJkKtCXRfzj9rxSyQrQJC XV6qsjLTgduEr1XAzqIbB05W2fChE4ELQTaAQ4HU8dy/o3H3rcXxHQieIccfO6xV0Cy3OIyynB6Pn cpUfBtMKcYF6sbKouEXOUX71HyX6XN4LepL+Ot4BnVGtIzVh8/3GJI6EM1+92aOeOowGLDTWcW0lP 1Z8b43xA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gSVjw-0005HB-QG; Thu, 29 Nov 2018 23:29:00 +0000 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gSVja-0004vG-Te; Thu, 29 Nov 2018 23:28:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1543534309; x=1575070309; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=i7g213jXuExf9WQ9ppjwE4Ycti2qAbTHczLIWdNAD5A=; b=hghfFBKXoNFoVlGIOnQKdcFFico1O7NbzOSdrYrvyoS/yhohqhDaCMF2 rcg4X5cbM78NJuheOGqYvLpUY2LPX8HpERL7YKoHu6S4I9fcCYUHXhKsi /i/74FLJ7FLnv1wbFoJ2GFLJ+5RQvfWiHS9F+l6bdFc4monijP68UQoDH YCWa8H/rik3DHIOX8tAel4+MkppAy/yCLpzoCL/1c2r5o5OWh1bgtGk7f qzzIWa5dCqScWQ+sytrLEvKRD4yOL8upRkezHf+Wel9LU5GA5NoisWAsV oXG+qKIE+zG/mFKfVtbfN/xS8ccA+KEWhX69CxGtltqDBQIwfgbjiX7DE A==; X-IronPort-AV: E=Sophos;i="5.56,296,1539619200"; d="scan'208";a="193267111" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Nov 2018 07:31:38 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 29 Nov 2018 15:11:28 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 29 Nov 2018 15:28:31 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [RFT PATCH v1 2/4] dt-binding: cpu-topology: Move cpu-map to a common binding. Date: Thu, 29 Nov 2018 15:28:18 -0800 Message-Id: <1543534100-3654-3-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543534100-3654-1-git-send-email-atish.patra@wdc.com> References: <1543534100-3654-1-git-send-email-atish.patra@wdc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181129_152838_998695_582BDDE8 X-CRM114-Status: GOOD ( 14.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "Rafael J. Wysocki" , "Peter Zijlstra \(Intel\)" , Catalin Marinas , Palmer Dabbelt , Will Deacon , Atish Patra , linux-riscv@lists.infradead.org, Morten Rasmussen , Juri Lelli , Dmitriy Cherkasov , Anup Patel , Ingo Molnar , devicetree@vger.kernel.org, Albert Ou , Rob Herring , Thomas Gleixner , "moderated list:ARM64 PORT AARCH64 ARCHITECTURE" , Ard Biesheuvel , Greg Kroah-Hartman , Jeremy Linton , Sudeep Holla MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found here. https://lkml.org/lkml/2018/11/6/19 Signed-off-by: Atish Patra Reviewed-by: Sudeep Holla --- .../{arm/topology.txt => cpu/cpu-topology.txt} | 81 ++++++++++++++++++---- 1 file changed, 67 insertions(+), 14 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (86%) diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/cpu/cpu-topology.txt similarity index 86% rename from Documentation/devicetree/bindings/arm/topology.txt rename to Documentation/devicetree/bindings/cpu/cpu-topology.txt index 66848355..1de6fbce 100644 --- a/Documentation/devicetree/bindings/arm/topology.txt +++ b/Documentation/devicetree/bindings/cpu/cpu-topology.txt @@ -1,12 +1,12 @@ =========================================== -ARM topology binding description +CPU topology binding description =========================================== =========================================== 1 - Introduction =========================================== -In an ARM system, the hierarchy of CPUs is defined through three entities that +In a SMP system, the hierarchy of CPUs is defined through three entities that are used to describe the layout of physical CPUs in the system: - socket @@ -14,9 +14,6 @@ are used to describe the layout of physical CPUs in the system: - core - thread -The cpu nodes (bindings defined in [1]) represent the devices that -correspond to physical CPUs and are to be mapped to the hierarchy levels. - The bottom hierarchy level sits at core or thread level depending on whether symmetric multi-threading (SMT) is supported or not. @@ -25,33 +22,37 @@ threads existing in the system and map to the hierarchy level "thread" above. In systems where SMT is not supported "cpu" nodes represent all cores present in the system and map to the hierarchy level "core" above. -ARM topology bindings allow one to associate cpu nodes with hierarchical groups +CPU topology bindings allow one to associate cpu nodes with hierarchical groups corresponding to the system hierarchy; syntactically they are defined as device tree nodes. -The remainder of this document provides the topology bindings for ARM, based -on the Devicetree Specification, available from: +Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be +used for any other architecture as well. -https://www.devicetree.org/specifications/ +The remainder of this document provides the topology bindings for ARM/RISC-V, based +on the Devicetree Specification, available at [4]. + +The cpu nodes (bindings defined in [1] for ARM or [2] for RISC-V) represent the devices that +correspond to physical CPUs and are to be mapped to the hierarchy levels. If not stated otherwise, whenever a reference to a cpu node phandle is made its value must point to a cpu node compliant with the cpu node bindings as -documented in [1]. +documented in [1] or [3] for respective ISA. A topology description containing phandles to cpu nodes that are not compliant -with bindings standardized in [1] is therefore considered invalid. +with bindings standardized in [1] or [3] is therefore considered invalid. =========================================== 2 - cpu-map node =========================================== -The ARM CPU topology is defined within the cpu-map node, which is a direct +The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct child of the cpus node and provides a container where the actual topology nodes are listed. - cpu-map node - Usage: Optional - On ARM SMP systems provide CPUs topology to the OS. - ARM uniprocessor systems do not require a topology + Usage: Optional - On SMP systems provide CPUs topology to the OS. + Uniprocessor systems do not require a topology description and therefore should not define a cpu-map node. @@ -494,8 +495,60 @@ cpus { }; }; +Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) + +cpus { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540g", "sifive,fu500"; + model = "sifive,hifive-unleashed-a00"; + + ... + + cpu-map { + cluster0 { + core0 { + cpu = <&L12>; + }; + core1 { + cpu = <&L15>; + }; + core2 { + cpu0 = <&L18>; + }; + core3 { + cpu0 = <&L21>; + }; + }; + }; + + L12: cpu@1 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x1>; + } + + L15: cpu@2 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x2>; + } + L18: cpu@3 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x3>; + } + L21: cpu@4 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x4>; + } +}; =============================================================================== [1] ARM Linux kernel documentation Documentation/devicetree/bindings/arm/cpus.txt [2] Devicetree NUMA binding description Documentation/devicetree/bindings/numa.txt +[3] RISC-V Linux kernel documentation + Documentation/devicetree/bindings/riscv/cpus.txt +[4] https://www.devicetree.org/specifications/