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Mon, 17 Dec 2018 06:03:59 +0000 Received: from mout.gmx.net ([212.227.17.22]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gYm0R-00030W-R6 for linux-arm-kernel@lists.infradead.org; Mon, 17 Dec 2018 06:03:57 +0000 Received: from corona.crabdance.com ([173.228.106.209]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0MUHbK-1gyes32odu-00R3oy; Mon, 17 Dec 2018 07:03:34 +0100 Received: by corona.crabdance.com (Postfix, from userid 1001) id 9C5116E85602; Sun, 16 Dec 2018 22:03:25 -0800 (PST) From: Stefan Schaeckeler To: Rob Herring , Mark Rutland , Joel Stanley , Andrew Jeffery , Borislav Petkov , Mauro Carvalho Chehab , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-edac@vger.kernel.org Subject: [PATCH 2/2] dt-bindings: edac: Aspeed AST2500 Date: Sun, 16 Dec 2018 22:01:57 -0800 Message-Id: <1545026517-64069-3-git-send-email-schaecsn@gmx.net> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1545026517-64069-1-git-send-email-schaecsn@gmx.net> References: <1545026517-64069-1-git-send-email-schaecsn@gmx.net> X-Provags-ID: V03:K1:MyWwx3gGskanIwe0jDsnK8d7E2zY9k8gWtJXmZkccmuO4erj1bH ymZXIVv4zZXpdrndTR4X72/n37JJ7qxeGnMdaZG4/fVSami207jaxTziuxlinSR8sDrUcF+ qKRYixdG0GW3xr/0FGpi6FP2BYOHcxwtaDMW6wQfyTxWkZ+cpE8bNLAufo1ijQLUwRizkoq srDURXm9mVvzm8OBLovwA== X-UI-Out-Filterresults: notjunk:1;V03:K0:mbv8/CNPiQ4=:2oOK6ayD7ROsSVujygy+HQ 6F30PoDWGXHg97XU6G0IiIlb11FWywQLBMm6Zf5fCydDRb/bN/7AwxDU5gIeSlvKFQNHp9w5Z rmjsksZ4fURMxYA2OsKAKG3vTulI01MUVPYiZIVKxrGKULhAI91F6bOaM9OFIZa9GbFRzvPzB rcoFH9fazKYB/AAdy6WRh0umLYti8ruvmq2wrRQ8Rp53Q5MiIcF/e8HxLbme1ftrFaUoge69i DM70+TmOG2dkrMlhu1voDtQtkuQ5nRRPJ4M1wJ2JEcavk8R/cervefy/u4arZBKHEyB86dtSb JwzUWnBSHqrRPWlK20qKQnZ1FBSIcz67aRXNFOKRPTWeva7M80DhkN1mlHuEuj6RudB922/ez IHTu/YEO2psNtLz1NZSWXuHM4TC5KsZnTNqVEUJ/yOnR++JpDMAOmkV8+kO6jklN6nru0dpAB xVh9dPPMdn8smoJPobSHGcRtBzlYVN9gAS9KqWUu09L5SMpVnHIJFFD/cEppEADq4xcppQkxu Rt7No3xclgzmKjhpDDXOGw9LIr0/QPokHSU92U5EEr+tb6fA5MLuecx7io4NB85NOufJ35mNl fGaOVPmpW3ATBeJOSqbiAjQJ9zMik4urt9zMRCPwHept1x4x5QhMaaCpoO1o266CxitV+pBO3 vzDMBKcL1YIq+l8eu8U+twqpWHa2enXRb/cCwa6DZEhw+PdVMXwVOpEWD98ICeMe3iHCsnzlP VlT0Dx7GVeYX08nSQ0A00IuRQF+ifq9UQVPnbgPxqP9Q6pC7XUdu2ULY35vfwacMjEaNgKKGg O+GYfD4A1+Lct4AMxdNNr5GjT3PdqO4RwuNmPu0EKv0LBE+ZBDem3R/oN8O3gx7DY1u1mD4Cl DbqIhhvoRm5UaoQvilgfVnhjDRxIxNKS4fpDv1ag4= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181216_220356_238534_8EE80E3E X-CRM114-Status: GOOD ( 12.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan M Schaeckeler MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stefan M Schaeckeler Add support for the Aspeed AST2500 SoC EDAC driver. Signed-off-by: Stefan M Schaeckeler --- .../bindings/edac/aspeed-sdram-edac.txt | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt new file mode 100644 index 000000000000..57ba852883c7 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt @@ -0,0 +1,34 @@ +Aspeed AST2500 SoC EDAC device driver + +The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error +correction check). + +The memory controller supports SECDED (single bit error correction, double bit +error detection) and single bit error auto scrubbing by reserving 8 bits for +every 64 bit word (effectively reducing available memory to 8/9). + +First, ECC must be configured in u-boot. Then, this driver will expose error +counters via the edac kernel framework. + +A note on memory organization in ECC mode: every 512 bytes are followed by 64 +bytes of ECC codes. The address remapping is done in hardware and is fully +transparent to firmware and software. Because of this, ECC mode must be +configured in u-boot as part of the memory initialization as one can not switch +from one mode to another when executing in memory. + + + +Required properties: +- compatible: should be "aspeed,ast2500-sdram-edac" +- reg: sdram controller register set should be <0x1e6e0000 0x174> +- interrupts: should be AVIC interrupt #0 + + +Example: + + edac: sdram@1e6e0000 { + compatible = "aspeed,ast2500-sdram-edac"; + reg = <0x1e6e0000 0x174>; + interrupts = <0>; + status = "okay"; + };