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Received: from foss.arm.com ([217.140.101.70]) by casper.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gjPEs-0006H1-IQ for linux-arm-kernel@lists.infradead.org; Tue, 15 Jan 2019 13:58:48 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AA758A78; Tue, 15 Jan 2019 05:58:45 -0800 (PST) Received: from e112298-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D50F33F70D; Tue, 15 Jan 2019 05:58:43 -0800 (PST) From: Julien Thierry To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 4/4] arm64: uaccess: Implement user_access_region_active Date: Tue, 15 Jan 2019 13:58:29 +0000 Message-Id: <1547560709-56207-5-git-send-email-julien.thierry@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1547560709-56207-1-git-send-email-julien.thierry@arm.com> References: <1547560709-56207-1-git-send-email-julien.thierry@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190115_135846_754906_07495440 X-CRM114-Status: GOOD ( 10.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julien Thierry , peterz@infradead.org, catalin.marinas@arm.com, will.deacon@arm.com, mingo@redhat.com, james.morse@arm.com, hpa@zytor.com, valentin.schneider@arm.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Provide arm64 implementation of user_access_region_active. Check the status of PAN or SW PAN if needed. Signed-off-by: Julien Thierry Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/include/asm/sysreg.h | 2 ++ arch/arm64/include/asm/uaccess.h | 12 ++++++++++++ 2 files changed, 14 insertions(+) -- 1.9.1 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 72dc4c0..f0b2f32 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -114,6 +114,8 @@ #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) +#define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3) + #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 6a70c75..1a8acc9 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -225,6 +225,18 @@ static inline void uaccess_enable_not_uao(void) __uaccess_enable(ARM64_ALT_PAN_NOT_UAO); } +#define unsafe_user_region_active uaccess_region_active +static inline bool uaccess_region_active(void) +{ + if (system_uses_ttbr0_pan()) { + return read_sysreg(ttbr1_el1) & TTBR_ASID_MASK; + } else if (cpus_have_const_cap(ARM64_ALT_PAN_NOT_UAO) && + alternatives_applied) { + return !read_sysreg_s(SYS_PSTATE_PAN); + } + return false; +} + /* * Sanitise a uaccess pointer such that it becomes NULL if above the * current addr_limit.