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Thu, 17 Jan 2019 16:40:24 +0000 Received: from mout.gmx.net ([212.227.15.15]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gkAiK-0005oS-Nw for linux-arm-kernel@lists.infradead.org; Thu, 17 Jan 2019 16:40:22 +0000 Received: from corona.crabdance.com ([173.228.106.209]) by mail.gmx.com (mrgmx001 [212.227.17.190]) with ESMTPSA (Nemesis) id 0Ma1tv-1gWkYp0Wqt-00LjM3; Thu, 17 Jan 2019 17:40:08 +0100 Received: by corona.crabdance.com (Postfix, from userid 1001) id 1A3A36E85602; Thu, 17 Jan 2019 08:40:02 -0800 (PST) From: Stefan Schaeckeler To: Rob Herring , Mark Rutland , Joel Stanley , Andrew Jeffery , Borislav Petkov , Mauro Carvalho Chehab , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-edac@vger.kernel.org Subject: [PATCH v2 2/2] dt-bindings: edac: Aspeed AST2500 Date: Thu, 17 Jan 2019 08:38:17 -0800 Message-Id: <1547743097-5236-3-git-send-email-schaecsn@gmx.net> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1547743097-5236-1-git-send-email-schaecsn@gmx.net> References: <1547743097-5236-1-git-send-email-schaecsn@gmx.net> X-Provags-ID: V03:K1:acREAI7ia05S8qqj43tkSIgjpuCXQAGBmeAKzACUxCAVYTi+eXo ntxrFUPgKUBicdHgY4+qrujF7o2Bnytl3PtEL4GIajryYUxWf3z+zFpY6uUAGplStL5aHto JgRPzjMipoX8jCq4f6E2GrdkSQ+454TqAOBvYa2/gpgsk6ih/xUo7c8FjNJwTwMug0pMqx6 24F92KVl+Dhq4yBk3KG3A== X-UI-Out-Filterresults: notjunk:1;V03:K0:kSLD9qsKXwE=:9bnK4X4LFcgg+8EfZyr1/S H49IljoobZeWJLJ2k7Uz4ccrcN3Uvv9vEI+i3wM6UVRYAw7WDzGLkClB7yG4XzAc+vXE2ivXd Azwa9Ol0EFgrj/YVCrM3upLiVT6GeXWm0wMxaa48dZBlVwPbZe/qOBWDd3AMVwhQy0F4/sPd2 0ADTc9g6/l5+rj4ycCvIDIj+Zlnv6VV33g3rbeOfQ7Y2dNjM5mhsdAsj3XvUsWpFoGtIzPPE3 G5WYOCDmucd9pq0Ufxxu3v796+ZPqHp7j2q/825E3Jjqjgc6KJd63zb7GnBzX/oiii7N0O5AC YUuyNGApd+ciXcu3f9K0HgYC08RbZSckW+xImmrsf/b+F/B3pkO65T81v4pZqbAYjnR1hZbQL JV6poeNOhvhlP5TLoST8tqICPSqcwJzKmX1iPNAyCGHoYZS2ZpY2aQEou8YBmWlhgu379XYih P5AGDZeKXfuKba8+XBa4X70UxUNSTKt5Dwvkat/0rU6s2vtYBaMR5qKGV+TC6L9+1FprHAqUD +CuM1i2xfXvDz+XoAoYpX+janc2ObMRuaOfyTanderCz64srZk7pt1TnjXmSaGsR4CgFlekwp zwOwtkB2KDyMOQfotDkPcbHAlXBrtZiCOsazVGe9DPjI2OrRSGhMOai+X3lcSTEFNwwxKfIc7 3SHC0HY0avxgSr1pMQIDytvWD8fQSyqrwBpapFXay1UES8y/sKrl6HvcEhO/tw9LC3pl/40L3 QU0Ftq+/KKEu+aPMFxngQ2ug3c99896lGhd9wNusGj0G1xDPShqjIuWxitKKa/gpmCuItuiMa iNE2U7GYOEKIND8wq6PFiMAO+SBmhmCAwdwleVnRtlpopQoM+zLFlqPNyG7DLAuH4wZosrBtH FFEbIMu0TzkigzPgcFmMXvM3/VudevnBWFnXFCN/YSXMYD5YeQmqHhq0966q8N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190117_084021_212474_11BC9D63 X-CRM114-Status: GOOD ( 11.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan M Schaeckeler MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stefan M Schaeckeler Add support for EDAC on the Aspeed AST2500 SoC. Signed-off-by: Stefan M Schaeckeler Reviewed-by: Andrew Jeffery --- .../bindings/edac/aspeed-sdram-edac.txt | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt new file mode 100644 index 000000000000..6a0f3d90d682 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt @@ -0,0 +1,25 @@ +Aspeed AST2500 SoC EDAC node + +The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error +correction check). + +The memory controller supports SECDED (single bit error correction, double bit +error detection) and single bit error auto scrubbing by reserving 8 bits for +every 64 bit word (effectively reducing available memory to 8/9). + +Note, the bootloader must configure ECC mode in the memory controller. + + +Required properties: +- compatible: should be "aspeed,ast2500-sdram-edac" +- reg: sdram controller register set should be <0x1e6e0000 0x174> +- interrupts: should be AVIC interrupt #0 + + +Example: + + edac: sdram@1e6e0000 { + compatible = "aspeed,ast2500-sdram-edac"; + reg = <0x1e6e0000 0x174>; + interrupts = <0>; + };