| Message ID | 1548084825-8803-8-git-send-email-julien.thierry@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: provide pseudo NMI with GICv3 | expand |
On Mon, 21 Jan 2019 15:33:26 +0000, Julien Thierry <julien.thierry@arm.com> wrote: > > Introduce fixed values for PMR that are going to be used to mask and > unmask interrupts by priority. > > The current priority given to GIC interrupts is 0xa0, so clearing PMR's > most significant bit is enough to mask interrupts. > > Signed-off-by: Julien Thierry <julien.thierry@arm.com> > Suggested-by: Daniel Thompson <daniel.thompson@linaro.org> > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > Cc: Oleg Nesterov <oleg@redhat.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will.deacon@arm.com> > --- > arch/arm64/include/asm/ptrace.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h > index fce22c4..05cf913 100644 > --- a/arch/arm64/include/asm/ptrace.h > +++ b/arch/arm64/include/asm/ptrace.h > @@ -25,6 +25,18 @@ > #define CurrentEL_EL1 (1 << 2) > #define CurrentEL_EL2 (2 << 2) > > +/* > + * PMR values used to mask/unmask interrupts. > + * > + * GIC priority masking works as follows: if an IRQ's priority is a higher value > + * than the value held in PMR, that interrupt is masked. A lower value of PMR > + * means more IRQ priorities are masked. Nit: It is not the priorities that are masked, but interrupts that have a priority higher than that of PMR. > + * > + * To mask priorities, we clear the most significant bit of PMR. > + */ > +#define GIC_PRIO_IRQON 0xf0 > +#define GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80) > + > /* Additional SPSR bits not exposed in the UABI */ > #define PSR_IL_BIT (1 << 20) > > -- > 1.9.1 > Otherwise: Acked-by: Marc Zyngier <marc.zyngier@arm.com> M.
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index fce22c4..05cf913 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -25,6 +25,18 @@ #define CurrentEL_EL1 (1 << 2) #define CurrentEL_EL2 (2 << 2) +/* + * PMR values used to mask/unmask interrupts. + * + * GIC priority masking works as follows: if an IRQ's priority is a higher value + * than the value held in PMR, that interrupt is masked. A lower value of PMR + * means more IRQ priorities are masked. + * + * To mask priorities, we clear the most significant bit of PMR. + */ +#define GIC_PRIO_IRQON 0xf0 +#define GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80) + /* Additional SPSR bits not exposed in the UABI */ #define PSR_IL_BIT (1 << 20)