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Wed, 13 Feb 2019 19:05:12 +0000 From: Abel Vesa To: Rob Herring , Stephen Boyd , Mark Rutland , Mike Turquette , Shawn Guo , Sascha Hauer , Lucas Stach , Angus Ainslie , Anson Huang Subject: [RFC 1/5] clk: imx: imx8mq: Fix the rate propagation for arm pll Thread-Topic: [RFC 1/5] clk: imx: imx8mq: Fix the rate propagation for arm pll Thread-Index: AQHUw88Lx/34yAmb5k+9Wv1v0WwQCQ== Date: Wed, 13 Feb 2019 19:05:12 +0000 Message-ID: <1550084693-9797-2-git-send-email-abel.vesa@nxp.com> References: <1550084693-9797-1-git-send-email-abel.vesa@nxp.com> In-Reply-To: <1550084693-9797-1-git-send-email-abel.vesa@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0058.eurprd07.prod.outlook.com (2603:10a6:203:2::20) To AM0PR04MB5779.eurprd04.prod.outlook.com (2603:10a6:208:131::23) x-originating-ip: [95.76.156.53] authentication-results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1d0c03d7-6585-4249-6d04-08d691e62e1f x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Fixes: b80522040cd3f ("clk: imx: Add clock driver for i.MX8MQ CCM") Signed-off-by: Abel Vesa Reviewed-by: Lucas Stach --- drivers/clk/imx/clk-imx8mq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 398ab0b..57499ed 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -340,7 +340,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) clks[IMX8MQ_DRAM_PLL2_DIV] = imx_clk_divider("dram_pll2_div", "dram_pll2", base + 0x68, 1, 6); /* PLL bypass out */ - clks[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_mux("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels)); + clks[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); clks[IMX8MQ_GPU_PLL_BYPASS] = imx_clk_mux("gpu_pll_bypass", base + 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels)); clks[IMX8MQ_VPU_PLL_BYPASS] = imx_clk_mux("vpu_pll_bypass", base + 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels)); clks[IMX8MQ_AUDIO_PLL1_BYPASS] = imx_clk_mux("audio_pll1_bypass", base + 0x0, 14, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels));