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Thu, 14 Feb 2019 01:54:01 +0000 From: Anson Huang To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "mturquette@baylibre.com" , "sboyd@kernel.org" , Aisheng Dong , Daniel Baluta , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "viresh.kumar@linaro.org" Subject: [PATCH V4 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table Thread-Topic: [PATCH V4 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table Thread-Index: AQHUxAgoEGMMDf+QVUa0wIDEs6tvwg== Date: Thu, 14 Feb 2019 01:54:01 +0000 Message-ID: <1550108915-574-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR02CA0163.apcprd02.prod.outlook.com (2603:1096:201:1f::23) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dl-linux-imx Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add i.MX8QXP CPU opp table to support cpufreq. Signed-off-by: Anson Huang --- No change since V3. --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 4021f25..593e2db 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -34,6 +34,10 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; + clocks = <&clk IMX_A35_CLK>; + clock-latency = <61036>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_0_opp_table>; }; A35_1: cpu@1 { @@ -42,6 +46,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; + operating-points-v2 = <&a35_0_opp_table>; }; A35_2: cpu@2 { @@ -50,6 +55,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&A35_L2>; + operating-points-v2 = <&a35_0_opp_table>; }; A35_3: cpu@3 { @@ -58,6 +64,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&A35_L2>; + operating-points-v2 = <&a35_0_opp_table>; }; A35_L2: l2-cache0 { @@ -65,6 +72,24 @@ }; }; + a35_0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */