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Thu, 21 Feb 2019 18:25:34 +0000 From: Aisheng Dong To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH 11/14] arm64: dts: imx8: split adma ss into dma and audio ss Thread-Topic: [PATCH 11/14] arm64: dts: imx8: split adma ss into dma and audio ss Thread-Index: AQHUyhLVa4voSQ/PHE68eEoO39rJ3g== Date: Thu, 21 Feb 2019 18:25:34 +0000 Message-ID: <1550773093-13349-12-git-send-email-aisheng.dong@nxp.com> References: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR03CA0051.apcprd03.prod.outlook.com (2603:1096:202:17::21) To VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:3e::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 73520381-a397-4795-3dcd-08d69829f844 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Let's split them into two ss for better code reuse. Signed-off-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 274 +------------------- arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 279 +++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 +- arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi | 10 +- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +- 5 files changed, 288 insertions(+), 281 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi index 835ecf7..991aaab 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -4,276 +4,4 @@ * Dong Aisheng */ -#include - -adma_subsys: bus@59000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x59000000 0x0 0x59000000 0x2000000>; - - /* SCU clocks */ - adma_ipg_clk: clock-adma-ipg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <120000000>; - clock-output-names = "adma_ipg_clk"; - }; - - adc0_clk: clock-adc0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "adc0_clk"; - }; - - can0_clk: clock-can0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "can0_clk"; - }; - - ftm0_clk: clock-ftm0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "ftm0_clk"; - }; - - ftm1_clk: clock-ftm1 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "ftm1_clk"; - }; - - i2c0_clk: clock-i2c0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "i2c0_clk"; - }; - - i2c1_clk: clock-i2c1 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "i2c1_clk"; - }; - - i2c2_clk: clock-i2c2 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "i2c2_clk"; - }; - - i2c3_clk: clock-i2c3 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "i2c3_clk"; - }; - - lcd0_clk: clock-lcd0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "lcd0_clk"; - }; - - lcd0_pwm0_clk: clock-lcd0-pwm0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "lcd0_pwm0_clk"; - }; - - spi0_clk: clock-spi0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "spi0_clk"; - }; - - spi1_clk: clock-spi1 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "spi1_clk"; - }; - - spi2_clk: clock-spi2 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "spi2_clk"; - }; - - spi3_clk: clock-spi3 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "spi3_clk"; - }; - - uart0_clk: clock-uart0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "uart0_clk"; - }; - - uart1_clk: clock-uart1 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "uart1_clk"; - }; - - uart2_clk: clock-uart2 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "uart2_clk"; - }; - - uart3_clk: clock-uart3 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "uart3_clk"; - }; - - /* LPCG clocks */ - uart0_lpcg: clock-controller@5a460000 { - reg = <0x5a460000 0x10000>; - #clock-cells = <1>; - clocks = <&uart0_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "uart0_lpcg_baud_clk", - "uart0_lpcg_ipg_clk"; - }; - - uart1_lpcg: clock-controller@5a470000 { - reg = <0x5a470000 0x10000>; - #clock-cells = <1>; - clocks = <&uart1_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "uart1_lpcg_baud_clk", - "uart1_lpcg_ipg_clk"; - }; - - uart2_lpcg: clock-controller@5a480000 { - reg = <0x5a480000 0x10000>; - #clock-cells = <1>; - clocks = <&uart2_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "uart2_lpcg_baud_clk", - "uart2_lpcg_ipg_clk"; - }; - - uart3_lpcg: clock-controller@5a490000 { - reg = <0x5a490000 0x10000>; - #clock-cells = <1>; - clocks = <&uart3_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "uart3_lpcg_baud_clk", - "uart3_lpcg_ipg_clk"; - }; - - i2c0_lpcg: clock-controller@5ac00000 { - reg = <0x5ac00000 0x10000>; - #clock-cells = <1>; - clocks = <&i2c0_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "i2c0_lpcg_clk", - "i2c0_lpcg_ipg_clk"; - }; - - i2c1_lpcg: clock-controller@5ac10000 { - reg = <0x5ac10000 0x10000>; - #clock-cells = <1>; - clocks = <&i2c1_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "i2c1_lpcg_clk", - "i2c1_lpcg_ipg_clk"; - }; - - i2c2_lpcg: clock-controller@5ac20000 { - reg = <0x5ac20000 0x10000>; - #clock-cells = <1>; - clocks = <&i2c2_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "i2c2_lpcg_clk", - "i2c2_lpcg_ipg_clk"; - }; - - i2c3_lpcg: clock-controller@5ac30000 { - reg = <0x5ac30000 0x10000>; - #clock-cells = <1>; - clocks = <&i2c3_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "i2c3_lpcg_clk", - "i2c3_lpcg_ipg_clk"; - }; - - adma_lpuart0: serial@5a060000 { - reg = <0x5a060000 0x1000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&uart0_lpcg 0>; - clock-names = "ipg"; - power-domains = <&pd IMX_SC_R_UART_0>; - status = "disabled"; - }; - - adma_i2c0: i2c@5a800000 { - reg = <0x5a800000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&i2c0_lpcg 0>; - clock-names = "per"; - assigned-clocks = <&i2c0_clk>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_0>; - status = "disabled"; - }; - - adma_i2c1: i2c@5a810000 { - reg = <0x5a810000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&i2c1_lpcg 0>; - clock-names = "per"; - assigned-clocks = <&i2c1_clk>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_1>; - status = "disabled"; - }; - - adma_i2c2: i2c@5a820000 { - reg = <0x5a820000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&i2c2_lpcg 0>; - clock-names = "per"; - assigned-clocks = <&i2c2_clk>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_2>; - status = "disabled"; - }; - - adma_i2c3: i2c@5a830000 { - reg = <0x5a830000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&i2c3_lpcg 0>; - clock-names = "per"; - assigned-clocks = <&i2c3_clk>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_3>; - status = "disabled"; - }; -}; +#include "imx8-ss-dma.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi new file mode 100644 index 0000000..fda5fa7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +#include + +dma_subsys: bus@5a000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; + + /* SCU clocks */ + dma_ipg_clk: clock-dma-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "dma_ipg_clk"; + }; + + adc0_clk: clock-adc0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "adc0_clk"; + }; + + can0_clk: clock-can0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "can0_clk"; + }; + + ftm0_clk: clock-ftm0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "ftm0_clk"; + }; + + ftm1_clk: clock-ftm1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "ftm1_clk"; + }; + + i2c0_clk: clock-i2c0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c0_clk"; + }; + + i2c1_clk: clock-i2c1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c1_clk"; + }; + + i2c2_clk: clock-i2c2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c2_clk"; + }; + + i2c3_clk: clock-i2c3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c3_clk"; + }; + + lcd0_clk: clock-lcd0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "lcd0_clk"; + }; + + lcd0_pwm0_clk: clock-lcd0-pwm0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "lcd0_pwm0_clk"; + }; + + spi0_clk: clock-spi0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi0_clk"; + }; + + spi1_clk: clock-spi1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi1_clk"; + }; + + spi2_clk: clock-spi2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi2_clk"; + }; + + spi3_clk: clock-spi3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi3_clk"; + }; + + uart0_clk: clock-uart0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart0_clk"; + }; + + uart1_clk: clock-uart1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart1_clk"; + }; + + uart2_clk: clock-uart2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart2_clk"; + }; + + uart3_clk: clock-uart3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart3_clk"; + }; + + /* LPCG clocks */ + uart0_lpcg: clock-controller@5a460000 { + reg = <0x5a460000 0x10000>; + #clock-cells = <1>; + clocks = <&uart0_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart0_lpcg_baud_clk", + "uart0_lpcg_ipg_clk"; + }; + + uart1_lpcg: clock-controller@5a470000 { + reg = <0x5a470000 0x10000>; + #clock-cells = <1>; + clocks = <&uart1_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart1_lpcg_baud_clk", + "uart1_lpcg_ipg_clk"; + }; + + uart2_lpcg: clock-controller@5a480000 { + reg = <0x5a480000 0x10000>; + #clock-cells = <1>; + clocks = <&uart2_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart2_lpcg_baud_clk", + "uart2_lpcg_ipg_clk"; + }; + + uart3_lpcg: clock-controller@5a490000 { + reg = <0x5a490000 0x10000>; + #clock-cells = <1>; + clocks = <&uart3_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart3_lpcg_baud_clk", + "uart3_lpcg_ipg_clk"; + }; + + i2c0_lpcg: clock-controller@5ac00000 { + reg = <0x5ac00000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c0_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c0_lpcg_clk", + "i2c0_lpcg_ipg_clk"; + }; + + i2c1_lpcg: clock-controller@5ac10000 { + reg = <0x5ac10000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c1_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c1_lpcg_clk", + "i2c1_lpcg_ipg_clk"; + }; + + i2c2_lpcg: clock-controller@5ac20000 { + reg = <0x5ac20000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c2_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c2_lpcg_clk", + "i2c2_lpcg_ipg_clk"; + }; + + i2c3_lpcg: clock-controller@5ac30000 { + reg = <0x5ac30000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c3_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c3_lpcg_clk", + "i2c3_lpcg_ipg_clk"; + }; + + dma_lpuart0: serial@5a060000 { + reg = <0x5a060000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&uart0_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_UART_0>; + status = "disabled"; + }; + + dma_i2c0: i2c@5a800000 { + reg = <0x5a800000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c0_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&i2c0_clk>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_0>; + status = "disabled"; + }; + + dma_i2c1: i2c@5a810000 { + reg = <0x5a810000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c1_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&i2c1_clk>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_1>; + status = "disabled"; + }; + + dma_i2c2: i2c@5a820000 { + reg = <0x5a820000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c2_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&i2c2_clk>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_2>; + status = "disabled"; + }; + + dma_i2c3: i2c@5a830000 { + reg = <0x5a830000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c3_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&i2c3_clk>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_3>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 03aad66..1f9c2f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -12,7 +12,7 @@ compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; chosen { - stdout-path = &adma_lpuart0; + stdout-path = &dma_lpuart0; }; memory@80000000 { @@ -30,7 +30,7 @@ }; }; -&adma_lpuart0 { +&dma_lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi index 2368e52..67b8807 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -108,22 +108,22 @@ compatible = "fsl,imx8qxp-lpcg"; }; -&adma_lpuart0 { +&dma_lpuart0 { compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; }; -&adma_i2c0 { +&dma_i2c0 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; }; -&adma_i2c1 { +&dma_i2c1 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; }; -&adma_i2c2 { +&dma_i2c2 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; }; -&adma_i2c3 { +&dma_i2c3 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 589483a..161f6c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -20,7 +20,7 @@ mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; - serial0 = &adma_lpuart0; + serial0 = &dma_lpuart0; }; cpus {