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Thu, 21 Feb 2019 18:24:56 +0000 From: Aisheng Dong To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH 02/14] arm64: dts: imx8: add lsio scu clocks Thread-Topic: [PATCH 02/14] arm64: dts: imx8: add lsio scu clocks Thread-Index: AQHUyhK+E717Y1+vT0iGHzMoJNdm+Q== Date: Thu, 21 Feb 2019 18:24:56 +0000 Message-ID: <1550773093-13349-3-git-send-email-aisheng.dong@nxp.com> References: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR03CA0051.apcprd03.prod.outlook.com (2603:1096:202:17::21) To VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:3e::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 36ce17f0-86d8-4ee6-d588-08d69829e145 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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#address-cells = <1>; #size-cells = <1>; ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; + /* SCU clocks */ + lsio_mem_clk: clock-lsio-mem { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "lsio_mem_clk"; + }; + + lsio_bus_clk: clock-lsio-bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "lsio_bus_clk"; + }; + + fspi0_clk: clock-fspi0{ + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "fspi0_clk"; + }; + + fspi1_clk: clock-fspi1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "fspi1_clk"; + }; + + gpt0_clk: clock-gpt0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpt0_clk"; + }; + + gpt1_clk: clock-gpt1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpt1_clk"; + }; + + gpt2_clk: clock-gpt2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpt2_clk"; + }; + + gpt3_clk: clock-gpt3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpt3_clk"; + }; + + gpt4_clk: clock-gpt4 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpt4_clk"; + }; + + pwm0_clk: clock-pwm0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm0_clk"; + }; + + pwm1_clk: clock-pwm1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm1_clk"; + }; + + pwm2_clk: clock-pwm2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm2_clk"; + }; + + pwm3_clk: clock-pwm3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm3_clk"; + }; + + pwm4_clk: clock-pwm4 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm4_clk"; + }; + + pwm5_clk: clock-pwm5 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm5_clk"; + }; + + pwm6_clk: clock-pwm6 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm6_clk"; + }; + + pwm7_clk: clock-pwm7 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm7_clk"; + }; + lsio_lpcg: clock-controller@5d400000 { reg = <0x5d400000 0x400000>; #clock-cells = <1>;