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Thu, 21 Feb 2019 18:25:04 +0000 From: Aisheng Dong To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH 04/14] arm64: dts: imx8: add adma scu clocks Thread-Topic: [PATCH 04/14] arm64: dts: imx8: add adma scu clocks Thread-Index: AQHUyhLEuW5LhJnxz0mCtv38lTB1nQ== Date: Thu, 21 Feb 2019 18:25:04 +0000 Message-ID: <1550773093-13349-5-git-send-email-aisheng.dong@nxp.com> References: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR03CA0051.apcprd03.prod.outlook.com (2603:1096:202:17::21) To VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:3e::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 019a81ab-77be-4e86-63a8-08d69829e668 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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#address-cells = <1>; #size-cells = <1>; ranges = <0x59000000 0x0 0x59000000 0x2000000>; + /* SCU clocks */ + adma_ipg_clk: clock-adma-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "adma_ipg_clk"; + }; + + adc0_clk: clock-adc0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "adc0_clk"; + }; + + can0_clk: clock-can0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "can0_clk"; + }; + + ftm0_clk: clock-ftm0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "ftm0_clk"; + }; + + ftm1_clk: clock-ftm1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "ftm1_clk"; + }; + + i2c0_clk: clock-i2c0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c0_clk"; + }; + + i2c1_clk: clock-i2c1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c1_clk"; + }; + + i2c2_clk: clock-i2c2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c2_clk"; + }; + + i2c3_clk: clock-i2c3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c3_clk"; + }; + + lcd0_clk: clock-lcd0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "lcd0_clk"; + }; + + lcd0_pwm0_clk: clock-lcd0-pwm0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "lcd0_pwm0_clk"; + }; + + spi0_clk: clock-spi0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi0_clk"; + }; + + spi1_clk: clock-spi1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi1_clk"; + }; + + spi2_clk: clock-spi2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi2_clk"; + }; + + spi3_clk: clock-spi3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi3_clk"; + }; + + uart0_clk: clock-uart0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart0_clk"; + }; + + uart1_clk: clock-uart1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart1_clk"; + }; + + uart2_clk: clock-uart2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart2_clk"; + }; + + uart3_clk: clock-uart3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart3_clk"; + }; + adma_lpcg: clock-controller@59000000 { reg = <0x59000000 0x2000000>; #clock-cells = <1>;