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Thu, 21 Feb 2019 18:25:20 +0000 From: Aisheng Dong To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH 07/14] arm64: dts: imx8: add adma lpcg clocks Thread-Topic: [PATCH 07/14] arm64: dts: imx8: add adma lpcg clocks Thread-Index: AQHUyhLLxJLRRM/F8kSNs7GWqsRDCw== Date: Thu, 21 Feb 2019 18:25:17 +0000 Message-ID: <1550773093-13349-8-git-send-email-aisheng.dong@nxp.com> References: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR03CA0051.apcprd03.prod.outlook.com (2603:1096:202:17::21) To VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:3e::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 95fe7990-0911-414d-18a4-08d69829ee0e x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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}; + /* LPCG clocks */ + uart0_lpcg: clock-controller@5a460000 { + reg = <0x5a460000 0x10000>; + #clock-cells = <1>; + clocks = <&uart0_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart0_lpcg_baud_clk", + "uart0_lpcg_ipg_clk"; + }; + + uart1_lpcg: clock-controller@5a470000 { + reg = <0x5a470000 0x10000>; + #clock-cells = <1>; + clocks = <&uart1_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart1_lpcg_baud_clk", + "uart1_lpcg_ipg_clk"; + }; + + uart2_lpcg: clock-controller@5a480000 { + reg = <0x5a480000 0x10000>; + #clock-cells = <1>; + clocks = <&uart2_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart2_lpcg_baud_clk", + "uart2_lpcg_ipg_clk"; + }; + + uart3_lpcg: clock-controller@5a490000 { + reg = <0x5a490000 0x10000>; + #clock-cells = <1>; + clocks = <&uart3_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart3_lpcg_baud_clk", + "uart3_lpcg_ipg_clk"; + }; + + i2c0_lpcg: clock-controller@5ac00000 { + reg = <0x5ac00000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c0_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c0_lpcg_clk", + "i2c0_lpcg_ipg_clk"; + }; + + i2c1_lpcg: clock-controller@5ac10000 { + reg = <0x5ac10000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c1_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c1_lpcg_clk", + "i2c1_lpcg_ipg_clk"; + }; + + i2c2_lpcg: clock-controller@5ac20000 { + reg = <0x5ac20000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c2_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c2_lpcg_clk", + "i2c2_lpcg_ipg_clk"; + }; + + i2c3_lpcg: clock-controller@5ac30000 { + reg = <0x5ac30000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c3_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c3_lpcg_clk", + "i2c3_lpcg_ipg_clk"; + }; + adma_lpcg: clock-controller@59000000 { reg = <0x59000000 0x2000000>; #clock-cells = <1>;