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Thu, 21 Feb 2019 18:25:22 +0000 From: Aisheng Dong To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH 08/14] arm64: dts: imx8: switch to new clock binding Thread-Topic: [PATCH 08/14] arm64: dts: imx8: switch to new clock binding Thread-Index: AQHUyhLOMn/vTkPccUykcZOqFBROug== Date: Thu, 21 Feb 2019 18:25:22 +0000 Message-ID: <1550773093-13349-9-git-send-email-aisheng.dong@nxp.com> References: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR03CA0051.apcprd03.prod.outlook.com (2603:1096:202:17::21) To VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:3e::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6194847e-a528-407b-9a36-08d69829f09f x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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}; - adma_lpcg: clock-controller@59000000 { - reg = <0x59000000 0x2000000>; - #clock-cells = <1>; - }; - adma_lpuart0: serial@5a060000 { reg = <0x5a060000 0x1000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; + clocks = <&uart0_lpcg 0>; clock-names = "ipg"; power-domains = <&pd IMX_SC_R_UART_0>; status = "disabled"; @@ -238,9 +233,9 @@ adma_subsys: bus@59000000 { reg = <0x5a800000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; + clocks = <&i2c0_lpcg 0>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; + assigned-clocks = <&i2c0_clk>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_0>; status = "disabled"; @@ -250,9 +245,9 @@ adma_subsys: bus@59000000 { reg = <0x5a810000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; + clocks = <&i2c1_lpcg 0>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; + assigned-clocks = <&i2c1_clk>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_1>; status = "disabled"; @@ -262,9 +257,9 @@ adma_subsys: bus@59000000 { reg = <0x5a820000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; + clocks = <&i2c2_lpcg 0>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; + assigned-clocks = <&i2c2_clk>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_2>; status = "disabled"; @@ -274,9 +269,9 @@ adma_subsys: bus@59000000 { reg = <0x5a830000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; + clocks = <&i2c3_lpcg 0>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; + assigned-clocks = <&i2c3_clk>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_3>; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 33a3584..c6b2870 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -198,11 +198,11 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; + assigned-clocks = <&sdhc0_clk>; assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_0>; status = "disabled"; @@ -212,11 +212,11 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b020000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; + clocks = <&sdhc1_lpcg 1>, + <&sdhc1_lpcg 0>, + <&sdhc1_lpcg 2>; clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; + assigned-clocks = <&sdhc1_clk>; assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; @@ -228,11 +228,11 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b030000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; + clocks = <&sdhc2_lpcg 1>, + <&sdhc2_lpcg 0>, + <&sdhc2_lpcg 2>; clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; + assigned-clocks = <&sdhc2_clk>; assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_2>; status = "disabled"; @@ -244,10 +244,10 @@ conn_subsys: bus@5b000000 { , , ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; + clocks = <&enet0_lpcg 3>, + <&enet0_lpcg 2>, + <&enet0_lpcg 1>, + <&enet0_lpcg 0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; @@ -261,10 +261,10 @@ conn_subsys: bus@5b000000 { , , ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; + clocks = <&enet1_lpcg 3>, + <&enet1_lpcg 2>, + <&enet1_lpcg 1>, + <&enet1_lpcg 0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi index 2486c72..2368e52 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -4,8 +4,108 @@ * Dong Aisheng */ -&adma_lpcg { - compatible = "fsl,imx8qxp-lpcg-adma"; +&adc0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&can0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&ftm0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&ftm1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&i2c0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&i2c1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&i2c2_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&i2c3_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&lcd0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&lcd0_pwm0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&spi0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&spi1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&spi2_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&spi3_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&uart0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&uart1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&uart2_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&uart3_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&uart0_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&uart1_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&uart2_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&uart3_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&i2c0_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&i2c1_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&i2c2_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&i2c3_lpcg { + compatible = "fsl,imx8qxp-lpcg"; }; &adma_lpuart0 { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi index 27a3b46..5f6552d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi @@ -4,8 +4,72 @@ * Dong Aisheng */ -&conn_lpcg { - compatible = "fsl,imx8qxp-lpcg-conn"; +&enet0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&enet0_bypass_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&enet0_rgmii_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&enet1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&enet1_bypass_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&enet1_rgmii_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpmi_bch_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpmi_bch_io_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&sdhc0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&sdhc1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&usb3_aclk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&usb3_bus_aclk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&usb3_lpm_aclk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&sdhc0_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&sdhc1_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&enet0_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&enet1_lpcg { + compatible = "fsl,imx8qxp-lpcg"; }; &usdhc1 { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi index 842849b..742e57f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -4,8 +4,96 @@ * Dong Aisheng */ -&lsio_lpcg { - compatible = "fsl,imx8qxp-lpcg-lsio"; +&fspi0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&fspi1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpt0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpt1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpt2_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpt3_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpt4_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm2_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm3_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm4_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm5_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm6_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm7_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm0_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm1_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm2_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm3_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm4_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm5_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm6_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm7_lpcg { + compatible = "fsl,imx8qxp-lpcg"; }; &lsio_mu0 { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index c27043c..589483a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -97,13 +97,6 @@ &lsio_mu1 1 2 &lsio_mu1 1 3>; - clk: clock-controller { - compatible = "fsl,imx8qxp-clk"; - #clock-cells = <1>; - clocks = <&xtal32k &xtal24m>; - clock-names = "xtal_32KHz", "xtal_24Mhz"; - }; - iomuxc: pinctrl { compatible = "fsl,imx8qxp-iomuxc"; };