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Tue, 26 Feb 2019 10:11:02 +0000 From: Vabhav Sharma To: "sudeep.holla@arm.com" , "oss@buserror.net" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linuxppc-dev@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "rjw@rjwysocki.net" , "viresh.kumar@linaro.org" , "linux-clk@vger.kernel.org" , "linux-pm@vger.kernel.org" , "linux-kernel-owner@vger.kernel.org" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "gregkh@linuxfoundation.org" , "arnd@arndb.de" , "kstewart@linuxfoundation.org" , "yamada.masahiro@socionext.com" , Leo Li , "shawnguo@kernel.org" Subject: [PATCH v1 3/4] clk: qoriq: increase array size of cmux_to_group Thread-Topic: [PATCH v1 3/4] clk: qoriq: increase array size of cmux_to_group Thread-Index: AQHUzbuTW+87PyC8B0m+Dsh6bbDYrA== Date: Tue, 26 Feb 2019 10:11:02 +0000 Message-ID: <1551132245-6089-4-git-send-email-vabhav.sharma@nxp.com> References: <1551132245-6089-1-git-send-email-vabhav.sharma@nxp.com> In-Reply-To: <1551132245-6089-1-git-send-email-vabhav.sharma@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0011.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::21) To VI1PR04MB4800.eurprd04.prod.outlook.com (2603:10a6:803:53::29) authentication-results: spf=none (sender IP is ) smtp.mailfrom=vabhav.sharma@nxp.com; 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Added -1, terminated, entry for 4080_cmux_grpX. Signed-off-by: Yogesh Gaur Signed-off-by: Vabhav Sharma Acked-by: Stephen Boyd Acked-by: Scott Wood --- drivers/clk/clk-qoriq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index 5baa9e0..e75194a 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -79,7 +79,7 @@ struct clockgen_chipinfo { const struct clockgen_muxinfo *cmux_groups[2]; const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL]; void (*init_periph)(struct clockgen *cg); - int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */ + int cmux_to_group[NUM_CMUX+1]; /* array should be -1 terminated */ u32 pll_mask; /* 1 << n bit set if PLL n is valid */ u32 flags; /* CG_xxx */ }; @@ -601,7 +601,7 @@ static const struct clockgen_chipinfo chipinfo[] = { &p4080_cmux_grp1, &p4080_cmux_grp2 }, .cmux_to_group = { - 0, 0, 0, 0, 1, 1, 1, 1 + 0, 0, 0, 0, 1, 1, 1, 1, -1 }, .pll_mask = 0x1f, },