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[V12,1/4] dt-bindings: perf: imx8-ddr: add imx8qxp ddr performance monitor

Message ID 1556736193-29411-1-git-send-email-Frank.Li@nxp.com (mailing list archive)
State New, archived
Headers show
Series [V12,1/4] dt-bindings: perf: imx8-ddr: add imx8qxp ddr performance monitor | expand

Commit Message

Frank Li May 1, 2019, 6:43 p.m. UTC 
Added binding doc for imx8qxp ddr performance monitor

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---

Notes:
    No change from v10 to v12
    
    Change from v8 to v9
    * use 32bit address width
    
    No change from v4 to v8
    
    Change from v4 to v4
    * remove "standard xxx"
    
    Change from v2 to v3
    * ddr_pmu0 -> ddr-pmu

 .../devicetree/bindings/perf/fsl-imx-ddr.txt       | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
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Patch

diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
new file mode 100644
index 0000000..9b9cda6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
@@ -0,0 +1,22 @@ 
+* Freescale(NXP) IMX8 DDR performance monitor
+
+Required properties:
+
+- compatible: should be one of:
+	"fsl,imx8-ddr-pmu"
+	"fsl,imx8m-ddr-pmu"
+
+- reg: physical address and size
+
+- interrupts: single interrupt
+	generated by the control block
+
+Example:
+
+	ddr-pmu@5c020000 {
+		compatible = "fsl,imx8-ddr-pmu";
+		reg = <0x5c020000 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+	};
+