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Thu, 02 May 2019 10:10:18 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 046A831; Thu, 2 May 2019 08:10:17 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D060BEDE; Thu, 2 May 2019 08:10:17 +0000 (GMT) Received: from SAFEX1HUBCAS21.st.com (10.75.90.45) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 2 May 2019 10:10:17 +0200 Received: from localhost (10.129.4.86) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 2 May 2019 10:10:17 +0200 From: Fabien Dessenne To: Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Ohad Ben-Cohen , Bjorn Andersson , , , , , Subject: [PATCH v3 1/8] dt-bindings: stm32: add bindings for ML-AHB interconnect Date: Thu, 2 May 2019 10:09:59 +0200 Message-ID: <1556784606-3016-2-git-send-email-fabien.dessenne@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556784606-3016-1-git-send-email-fabien.dessenne@st.com> References: <1556784606-3016-1-git-send-email-fabien.dessenne@st.com> MIME-Version: 1.0 X-Originating-IP: [10.129.4.86] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-02_03:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190502_011026_780952_D1F95CD4 X-CRM114-Status: GOOD ( 14.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ludovic Barre , Arnaud Pouliquen , Loic Pallardy , Fabien Dessenne , Benjamin Gaignard Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Document the ML-AHB interconnect for stm32 SoCs. Signed-off-by: Fabien Dessenne --- .../devicetree/bindings/arm/stm32/mlahb.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/stm32/mlahb.txt diff --git a/Documentation/devicetree/bindings/arm/stm32/mlahb.txt b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt new file mode 100644 index 0000000..3f5b779 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt @@ -0,0 +1,37 @@ +ML-AHB interconnect bindings + +These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects +a Cortex-M subsystem with dedicated memories. +The MCU SRAM and RETRAM memory parts can be accessed through different addresses +(see "RAM aliases" in [1]) using different buses (see [2]) : balancing the +Cortex-M firmware accesses among those ports allows to tune the system +performance. + +[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf +[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping + +Required properties: +- compatible: should be "simple-bus" +- dma-ranges: describes memory addresses translation between the local CPU and + the remote Cortex-M processor. Each memory region, is declared with + 3 parameters: + - param 1: device base address (Cortex-M processor address) + - param 2: physical base address (local CPU address) + - param 3: size of the memory region. + +The Cortex-M remote processor accessed via the mlahb interconnect is described +by a child node. + +Example: +mlahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x38000000 0x10000>, + <0x10000000 0x10000000 0x60000>, + <0x30000000 0x30000000 0x60000>; + + m4_rproc: m4@38000000 { + ... + }; +};