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Mon, 20 May 2019 17:27:18 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3B47D38; Mon, 20 May 2019 15:27:17 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0BA022BAE; Mon, 20 May 2019 15:27:17 +0000 (GMT) Received: from SFHDAG5NODE1.st.com (10.75.127.13) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 20 May 2019 17:27:16 +0200 Received: from SFHDAG5NODE1.st.com ([fe80::cc53:528c:36c8:95f6]) by SFHDAG5NODE1.st.com ([fe80::cc53:528c:36c8:95f6%20]) with mapi id 15.00.1347.000; Mon, 20 May 2019 17:27:16 +0200 From: Gerald BAEZA To: "will.deacon@arm.com" , "mark.rutland@arm.com" , "robh+dt@kernel.org" , "mcoquelin.stm32@gmail.com" , Alexandre TORGUE , "corbet@lwn.net" , "linux@armlinux.org.uk" , "olof@lixom.net" , "horms+renesas@verge.net.au" , "arnd@arndb.de" Subject: [PATCH v2 2/5] dt-bindings: perf: stm32: ddrperfm support Thread-Topic: [PATCH v2 2/5] dt-bindings: perf: stm32: ddrperfm support Thread-Index: AQHVDyCBQQc7A9kqVEqkYhOzbDRQTg== Date: Mon, 20 May 2019 15:27:16 +0000 Message-ID: <1558366019-24214-3-git-send-email-gerald.baeza@st.com> References: <1558366019-24214-1-git-send-email-gerald.baeza@st.com> In-Reply-To: <1558366019-24214-1-git-send-email-gerald.baeza@st.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.45] MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-20_07:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_082740_718897_3710CA30 X-CRM114-Status: GOOD ( 14.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Gerald BAEZA , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The DDRPERFM is the DDR Performance Monitor embedded in STM32MP1 SOC. This documentation indicates how to enable stm32-ddr-pmu driver on DDRPERFM peripheral, via the device tree. Signed-off-by: Gerald Baeza Reviewed-by: Rob Herring --- .../devicetree/bindings/perf/stm32-ddr-pmu.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt diff --git a/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt new file mode 100644 index 0000000..9d36209 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt @@ -0,0 +1,20 @@ +* STM32 DDR Performance Monitor (DDRPERFM) + +Required properties: +- compatible: must be "st,stm32-ddr-pmu". +- reg: physical address and length of the registers set. +- clocks: list of phandles and specifiers to all input clocks listed in + clock-names property. +- clock-names: "bus" corresponds to the DDRPERFM bus clock and "ddr" to + the DDR frequency. +- resets: phandle to the reset controller and DDRPERFM reset specifier + +Example: + ddrperfm: perf@5a007000 { + compatible = "st,stm32-ddr-pmu"; + reg = <0x5a007000 0x400>; + clocks = <&rcc DDRPERFM>, <&rcc PLL2_R>; + clock-names = "bus", "ddr"; + resets = <&rcc DDRPERFM_R>; + }; +