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Mon, 20 May 2019 17:27:19 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A439034; Mon, 20 May 2019 15:27:18 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 73CBA2BAD; Mon, 20 May 2019 15:27:18 +0000 (GMT) Received: from SFHDAG5NODE1.st.com (10.75.127.13) by SFHDAG5NODE2.st.com (10.75.127.14) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 20 May 2019 17:27:18 +0200 Received: from SFHDAG5NODE1.st.com ([fe80::cc53:528c:36c8:95f6]) by SFHDAG5NODE1.st.com ([fe80::cc53:528c:36c8:95f6%20]) with mapi id 15.00.1347.000; Mon, 20 May 2019 17:27:17 +0200 From: Gerald BAEZA To: "will.deacon@arm.com" , "mark.rutland@arm.com" , "robh+dt@kernel.org" , "mcoquelin.stm32@gmail.com" , Alexandre TORGUE , "corbet@lwn.net" , "linux@armlinux.org.uk" , "olof@lixom.net" , "horms+renesas@verge.net.au" , "arnd@arndb.de" Subject: [PATCH v2 4/5] ARM: configs: enable STM32_DDR_PMU Thread-Topic: [PATCH v2 4/5] ARM: configs: enable STM32_DDR_PMU Thread-Index: AQHVDyCC+z9rDopJM0iiSqzcMwe2cA== Date: Mon, 20 May 2019 15:27:17 +0000 Message-ID: <1558366019-24214-5-git-send-email-gerald.baeza@st.com> References: <1558366019-24214-1-git-send-email-gerald.baeza@st.com> In-Reply-To: <1558366019-24214-1-git-send-email-gerald.baeza@st.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.45] MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-20_07:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_082740_619780_C5316CE4 X-CRM114-Status: GOOD ( 13.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Gerald BAEZA , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP STM32_DDR_PMU enables the perf driver that controls the DDR Performance Monitor (DDRPERFM) Signed-off-by: Gerald Baeza --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 6b748f2..059b1b9 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -1009,6 +1009,7 @@ CONFIG_PHY_DM816X_USB=m CONFIG_OMAP_USB2=y CONFIG_TI_PIPE3=y CONFIG_TWL4030_USB=m +CONFIG_STM32_DDR_PMU=m CONFIG_MESON_MX_EFUSE=m CONFIG_ROCKCHIP_EFUSE=m CONFIG_NVMEM_IMX_OCOTP=y