| Message ID | 1560138293-4163-1-git-send-email-weiyi.lu@mediatek.com (mailing list archive) |
|---|---|
| State | RFC |
| Headers | show |
| Series | [RFC,v1] clk: core: support clocks that need to be enabled during re-parent | expand |
On Mon, Jun 10, 2019 at 11:44:53AM +0800, Weiyi Lu wrote: > When using property assigned-clock-parents to assign parent clocks, > core clocks might still be disabled during re-parent. > Add flag 'CLK_OPS_CORE_ENABLE' for those clocks must be enabled > during re-parent. > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> > --- > drivers/clk/clk.c | 9 +++++++++ > include/linux/clk-provider.h | 1 + > 2 files changed, 10 insertions(+) <formletter> This is not the correct way to submit patches for inclusion in the stable kernel tree. Please read: https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html for how to do this properly. </formletter>
Quoting Weiyi Lu (2019-06-09 20:44:53) > When using property assigned-clock-parents to assign parent clocks, > core clocks might still be disabled during re-parent. > Add flag 'CLK_OPS_CORE_ENABLE' for those clocks must be enabled > during re-parent. > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Can you further describe the scenario where this is a problem? Is it some sort of clk that is enabled by default out of the bootloader and is then configured to have an 'assigned-clock-parents' property to change the parent, but that clk needs to be "enabled" so that the framework turns on the parents for the parent switch?
On Tue, 2019-06-25 at 15:14 -0700, Stephen Boyd wrote: > Quoting Weiyi Lu (2019-06-09 20:44:53) > > When using property assigned-clock-parents to assign parent clocks, > > core clocks might still be disabled during re-parent. > > Add flag 'CLK_OPS_CORE_ENABLE' for those clocks must be enabled > > during re-parent. > > > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> > > Can you further describe the scenario where this is a problem? Is it > some sort of clk that is enabled by default out of the bootloader and is > then configured to have an 'assigned-clock-parents' property to change > the parent, but that clk needs to be "enabled" so that the framework > turns on the parents for the parent switch? When driver is built as module(.ko) and install at runtime after the whole initialization stage. Clk might already be turned off before configuring by assigned-clock-parents. For such clock design that need to have clock enabled during re-parent, the configuration of assigned-clock-parents might be failed. That's the problem we have now. Do you have any suggestion for such usage of clocks? Many thanks. >
Quoting Weiyi Lu (2019-06-25 18:05:22) > On Tue, 2019-06-25 at 15:14 -0700, Stephen Boyd wrote: > > Quoting Weiyi Lu (2019-06-09 20:44:53) > > > When using property assigned-clock-parents to assign parent clocks, > > > core clocks might still be disabled during re-parent. > > > Add flag 'CLK_OPS_CORE_ENABLE' for those clocks must be enabled > > > during re-parent. > > > > > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> > > > > Can you further describe the scenario where this is a problem? Is it > > some sort of clk that is enabled by default out of the bootloader and is > > then configured to have an 'assigned-clock-parents' property to change > > the parent, but that clk needs to be "enabled" so that the framework > > turns on the parents for the parent switch? > > When driver is built as module(.ko) and install at runtime after the > whole initialization stage. Clk might already be turned off before > configuring by assigned-clock-parents. For such clock design that need > to have clock enabled during re-parent, the configuration of > assigned-clock-parents might be failed. That's the problem we have now. Great. Please put this sort of information in the commit text. > Do you have any suggestion for such usage of clocks? Many thanks. > Ok, and in this case somehow CLK_OPS_PARENT_ENABLE flag doesn't work? Is that because the clk itself doesn't do anything unless it's enabled? I seem to recall that we usually work around this by caching the state of the clk parents or frequencies and then when the clk prepare or enable op is called we actually write the hardware to change the state. There are some qcom clks like this and we basically just use the hardware itself to cache the state of the clk while it hasn't actually changed to be at that rate, because the clk is not enabled yet. The main concern is that we're having to turn on clks to make things work, when it would be best to not turn on clks just so that register writes actually make a difference to what the hardware does.
On Tue, 2019-06-25 at 20:52 -0700, Stephen Boyd wrote: > Quoting Weiyi Lu (2019-06-25 18:05:22) > > On Tue, 2019-06-25 at 15:14 -0700, Stephen Boyd wrote: > > > Quoting Weiyi Lu (2019-06-09 20:44:53) > > > > When using property assigned-clock-parents to assign parent clocks, > > > > core clocks might still be disabled during re-parent. > > > > Add flag 'CLK_OPS_CORE_ENABLE' for those clocks must be enabled > > > > during re-parent. > > > > > > > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> > > > > > > Can you further describe the scenario where this is a problem? Is it > > > some sort of clk that is enabled by default out of the bootloader and is > > > then configured to have an 'assigned-clock-parents' property to change > > > the parent, but that clk needs to be "enabled" so that the framework > > > turns on the parents for the parent switch? > > > > When driver is built as module(.ko) and install at runtime after the > > whole initialization stage. Clk might already be turned off before > > configuring by assigned-clock-parents. For such clock design that need > > to have clock enabled during re-parent, the configuration of > > assigned-clock-parents might be failed. That's the problem we have now. > > Great. Please put this sort of information in the commit text. > OK, I'll do when sending next version. > > Do you have any suggestion for such usage of clocks? Many thanks. > > > > Ok, and in this case somehow CLK_OPS_PARENT_ENABLE flag doesn't work? Is > that because the clk itself doesn't do anything unless it's enabled? I > seem to recall that we usually work around this by caching the state of > the clk parents or frequencies and then when the clk prepare or enable > op is called we actually write the hardware to change the state. There > are some qcom clks like this and we basically just use the hardware > itself to cache the state of the clk while it hasn't actually changed to > be at that rate, because the clk is not enabled yet. > Hi Stephen, Will you recommend if we cache the state in the platform driver instead of the hardware itself and then change the state when clk enable op is called if we don't have such hardware design on MTK clocks? > The main concern is that we're having to turn on clks to make things > work, when it would be best to not turn on clks just so that register > writes actually make a difference to what the hardware does. > In my view, it's a safe operation to enable clock shortly to make things work when its child clock is still disabled. What do you think?
Hi Stephen, On Tue, Jun 25, 2019 at 08:52:45PM -0700, Stephen Boyd wrote: > Quoting Weiyi Lu (2019-06-25 18:05:22) > > On Tue, 2019-06-25 at 15:14 -0700, Stephen Boyd wrote: > > > Quoting Weiyi Lu (2019-06-09 20:44:53) > > > > When using property assigned-clock-parents to assign parent clocks, > > > > core clocks might still be disabled during re-parent. > > > > Add flag 'CLK_OPS_CORE_ENABLE' for those clocks must be enabled > > > > during re-parent. > > > > > > > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> > > > > > > Can you further describe the scenario where this is a problem? Is it > > > some sort of clk that is enabled by default out of the bootloader and is > > > then configured to have an 'assigned-clock-parents' property to change > > > the parent, but that clk needs to be "enabled" so that the framework > > > turns on the parents for the parent switch? > > > > When driver is built as module(.ko) and install at runtime after the > > whole initialization stage. Clk might already be turned off before > > configuring by assigned-clock-parents. For such clock design that need > > to have clock enabled during re-parent, the configuration of > > assigned-clock-parents might be failed. That's the problem we have now. > > Great. Please put this sort of information in the commit text. > > > Do you have any suggestion for such usage of clocks? Many thanks. > > Ok, and in this case somehow CLK_OPS_PARENT_ENABLE flag doesn't work? Is > that because the clk itself doesn't do anything unless it's enabled? I > seem to recall that we usually work around this by caching the state of > the clk parents or frequencies and then when the clk prepare or enable > op is called we actually write the hardware to change the state. There > are some qcom clks like this and we basically just use the hardware > itself to cache the state of the clk while it hasn't actually changed to > be at that rate, because the clk is not enabled yet. I'm trying to move the fix to the clock driver itself. Do you have any pointer to such a clock that I can use as an example ? > The main concern is that we're having to turn on clks to make things > work, when it would be best to not turn on clks just so that register > writes actually make a difference to what the hardware does. I agree, it's best not to turn the clock on if we can avoid it.
Quoting Laurent Pinchart (2021-01-23 10:42:27) > Hi Stephen, > > On Tue, Jun 25, 2019 at 08:52:45PM -0700, Stephen Boyd wrote: > > Quoting Weiyi Lu (2019-06-25 18:05:22) > > > On Tue, 2019-06-25 at 15:14 -0700, Stephen Boyd wrote: > > > > Quoting Weiyi Lu (2019-06-09 20:44:53) > > > > > When using property assigned-clock-parents to assign parent clocks, > > > > > core clocks might still be disabled during re-parent. > > > > > Add flag 'CLK_OPS_CORE_ENABLE' for those clocks must be enabled > > > > > during re-parent. > > > > > > > > > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> > > > > > > > > Can you further describe the scenario where this is a problem? Is it > > > > some sort of clk that is enabled by default out of the bootloader and is > > > > then configured to have an 'assigned-clock-parents' property to change > > > > the parent, but that clk needs to be "enabled" so that the framework > > > > turns on the parents for the parent switch? > > > > > > When driver is built as module(.ko) and install at runtime after the > > > whole initialization stage. Clk might already be turned off before > > > configuring by assigned-clock-parents. For such clock design that need > > > to have clock enabled during re-parent, the configuration of > > > assigned-clock-parents might be failed. That's the problem we have now. > > > > Great. Please put this sort of information in the commit text. > > > > > Do you have any suggestion for such usage of clocks? Many thanks. > > > > Ok, and in this case somehow CLK_OPS_PARENT_ENABLE flag doesn't work? Is > > that because the clk itself doesn't do anything unless it's enabled? I > > seem to recall that we usually work around this by caching the state of > > the clk parents or frequencies and then when the clk prepare or enable > > op is called we actually write the hardware to change the state. There > > are some qcom clks like this and we basically just use the hardware > > itself to cache the state of the clk while it hasn't actually changed to > > be at that rate, because the clk is not enabled yet. > > I'm trying to move the fix to the clock driver itself. Do you have any > pointer to such a clock that I can use as an example ? This reminds me of some stuff we did in the qcom clk driver to handle shared clks. Look at clk_rcg2_shared_ops in drivers/clk/qcom/clk-rcg2.c for some more details. But there we have hardware that allows you to write new settings but not set the "go" bit that actually switches the mux/divider to a new rate. The non-linux entity using the clks doesn't care what rate the clk is running at, it needs to just make sure the clk turns on so it can do its thing. But the problem is the clk can be turned on and off at random and that gets the clk stuck, so we put the clk at some safe frequency that is always on (XO) and let the other side go wild. But to the kernel we want it to think the rate is still what it was set to, so we cache away the rate the kernel thinks in the hardware and don't set the "go" bit so that when we enable the clk again in linux it will reconfigure the clk to be the rate we want. If you don't have that hardware then I suppose you'll have to cache the register value in the set_rate clk op and return that cached value from recalc_rate but only write the register value on the prepare/enable path. Should be doable, but not a lot of fun! It may also be possible to have some clk flag that makes the core do this for you by calling the set_rate() call at the right time. > > > The main concern is that we're having to turn on clks to make things > > work, when it would be best to not turn on clks just so that register > > writes actually make a difference to what the hardware does. > > I agree, it's best not to turn the clock on if we can avoid it. >
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 443711f..b2e6fe3 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1717,6 +1717,10 @@ static struct clk_core *__clk_set_parent_before(struct clk_core *core, clk_core_prepare_enable(parent); } + /* enable core if CLK_OPS_CORE_ENABLE is set */ + if (core->flags & CLK_OPS_CORE_ENABLE) + clk_core_prepare_enable(core); + /* migrate prepare count if > 0 */ if (core->prepare_count) { clk_core_prepare_enable(parent); @@ -1744,6 +1748,10 @@ static void __clk_set_parent_after(struct clk_core *core, clk_core_disable_unprepare(old_parent); } + /* re-balance ref counting if CLK_OPS_CORE_ENABLE is set */ + if (core->flags & CLK_OPS_CORE_ENABLE) + clk_core_disable_unprepare(core); + /* re-balance ref counting if CLK_OPS_PARENT_ENABLE is set */ if (core->flags & CLK_OPS_PARENT_ENABLE) { clk_core_disable_unprepare(parent); @@ -2973,6 +2981,7 @@ static int clk_dump_show(struct seq_file *s, void *data) ENTRY(CLK_IS_CRITICAL), ENTRY(CLK_OPS_PARENT_ENABLE), ENTRY(CLK_DUTY_CYCLE_PARENT), + ENTRY(CLK_OPS_CORE_ENABLE), #undef ENTRY }; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index bb6118f..39a1fed 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -34,6 +34,7 @@ #define CLK_OPS_PARENT_ENABLE BIT(12) /* duty cycle call may be forwarded to the parent clock */ #define CLK_DUTY_CYCLE_PARENT BIT(13) +#define CLK_OPS_CORE_ENABLE BIT(14) /* core need enable during re-parent */ struct clk; struct clk_hw;
When using property assigned-clock-parents to assign parent clocks, core clocks might still be disabled during re-parent. Add flag 'CLK_OPS_CORE_ENABLE' for those clocks must be enabled during re-parent. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> --- drivers/clk/clk.c | 9 +++++++++ include/linux/clk-provider.h | 1 + 2 files changed, 10 insertions(+)