diff mbox series

ARM: mm: print L310 cache controller version

Message ID 1561384489-29906-1-git-send-email-f.suligoi@asem.it (mailing list archive)
State New, archived
Headers show
Series ARM: mm: print L310 cache controller version | expand

Commit Message

Flavio Suligoi June 24, 2019, 1:54 p.m. UTC 
The knowledge of the cache controller version
is very useful during the comparison of the performances
of similar boards, with similar CPU but different versions
of the L310 controller.

Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
 arch/arm/mm/cache-l2x0.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5b251c8..e5ac670 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -590,6 +590,34 @@  static void l2c310_configure(void __iomem *base)
 	if (revision >= L310_CACHE_ID_RTL_R3P0)
 		l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base,
 			      L310_POWER_CTRL);
+
+	/* Display L310 cache controller version */
+	switch (revision) {
+	case L310_CACHE_ID_RTL_R0P0:
+		pr_info("L2C-310 revision: r0p0\n");
+		break;
+	case L310_CACHE_ID_RTL_R1P0:
+		pr_info("L2C-310 revision: r1p0\n");
+		break;
+	case L310_CACHE_ID_RTL_R2P0:
+		pr_info("L2C-310 revision: r2p0\n");
+		break;
+	case L310_CACHE_ID_RTL_R3P0:
+		pr_info("L2C-310 revision: r3p0\n");
+		break;
+	case L310_CACHE_ID_RTL_R3P1:
+		pr_info("L2C-310 revision: r3p1\n");
+		break;
+	case L310_CACHE_ID_RTL_R3P1_50REL0:
+		pr_info("L2C-310 revision: r3p1 50 rel0\n");
+		break;
+	case L310_CACHE_ID_RTL_R3P2:
+		pr_info("L2C-310 revision: r3p2\n");
+		break;
+	case L310_CACHE_ID_RTL_R3P3:
+		pr_info("L2C-310 revision: r3p3\n");
+		break;
+	}
 }
 
 static int l2c310_starting_cpu(unsigned int cpu)