From patchwork Sun Nov 17 12:43:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 11248317 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D65006C1 for ; Sun, 17 Nov 2019 12:48:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B402B206F4 for ; Sun, 17 Nov 2019 12:48:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="nf0qDs+e" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B402B206F4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=rHRrCiG9MqqS3WfuEvX7s55WUN3TW/nTFi26reAD/a4=; b=nf0qDs+emEsfmsBkN5kqy40b9C WBJ21Ot49VdoLG4nVMv7CYZ5UAyZsivhQv4SSOlVqp/zLSzjrO/IJpo7Or9X/w691OwZ5iLKRLE4h S6KVikgE+ZIsCnu9UZ3XDllY34JZc99DQe56TFo/HF09b4kQn3qf3SMq1Ut8Y0/T+/yl6WdIR25c0 0mM0aSXiPccowWfHZaebdfjbZUme3YhiDNLR8bbCaAbfMabnWy05jcV3lRx7Fx9csmS06MMvTh4IN YFN57IOHchPyxjA5D2qXydLFFc+VFE7qjMz5e+jXw1/qAAK53oUBJoR0/YWC0Vmc+Mdw80UALZvNT UV96WPsg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iWJyY-0000Y3-3B; Sun, 17 Nov 2019 12:48:22 +0000 Received: from inva021.nxp.com ([92.121.34.21]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iWJwQ-0007IB-Rn for linux-arm-kernel@lists.infradead.org; Sun, 17 Nov 2019 12:46:14 +0000 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 91EA42000D2; Sun, 17 Nov 2019 13:46:09 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E24242007DA; Sun, 17 Nov 2019 13:46:03 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 53D0E402D0; Sun, 17 Nov 2019 20:45:57 +0800 (SGT) From: Dong Aisheng To: linux-arm-kernel@lists.infradead.org Subject: [PATCH RESEND v3 06/15] arm64: dts: imx8: add adma lpcg clocks Date: Sun, 17 Nov 2019 20:43:46 +0800 Message-Id: <1573994635-14479-7-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573994635-14479-1-git-send-email-aisheng.dong@nxp.com> References: <1573994635-14479-1-git-send-email-aisheng.dong@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191117_044611_181780_0A8B8CD1 X-CRM114-Status: UNSURE ( 8.50 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [92.121.34.21 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dong Aisheng , Mark Rutland , devicetree@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, Rob Herring , linux-imx@nxp.com, kernel@pengutronix.de, fabio.estevam@nxp.com, shawnguo@kernel.org, linux-clk@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add adma lpcg clocks Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- ChangeLog: v3->v4: * add missing lpcg headfile v2->v3: * update to use clock-indices property instead of bit-offset property v1->v2: * Use old SCU clock binding temporarily to avoid build warning due to SCU clock cell will be changed to 2. * add power domain property --- .../boot/dts/freescale/imx8-ss-adma.dtsi | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi index 28b8fc9a81d4..6bd194a98c36 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -4,17 +4,51 @@ * Dong Aisheng */ +#include +#include + adma_subsys: bus@59000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x59000000 0x0 0x59000000 0x2000000>; + dma_ipg_clk: clock-dma-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "dma_ipg_clk"; + }; + + /* LPCG clocks */ adma_lpcg: clock-controller@59000000 { reg = <0x59000000 0x2000000>; #clock-cells = <1>; }; + dsp_lpcg: clock-controller@59580000 { + reg = <0x59580000 0x10000>; + #clock-cells = <1>; + clocks = <&dma_ipg_clk>, + <&dma_ipg_clk>, + <&dma_ipg_clk>; + clock-indices = , , + ; + clock-output-names = "dsp_lpcg_adb_clk", + "dsp_lpcg_ipg_clk", + "dsp_lpcg_core_clk"; + power-domains = <&pd IMX_SC_R_DSP>; + }; + + dsp_ram_lpcg: clock-controller@59590000 { + reg = <0x59590000 0x10000>; + #clock-cells = <1>; + clocks = <&dma_ipg_clk>; + clock-indices = ; + clock-output-names = "dsp_ram_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_DSP_RAM>; + }; + adma_dsp: dsp@596e8000 { compatible = "fsl,imx8qxp-dsp"; reg = <0x596e8000 0x88000>; @@ -80,6 +114,50 @@ adma_subsys: bus@59000000 { status = "disabled"; }; + uart0_lpcg: clock-controller@5a460000 { + reg = <0x5a460000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_UART0_CLK>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "uart0_lpcg_baud_clk", + "uart0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_0>; + }; + + uart1_lpcg: clock-controller@5a470000 { + reg = <0x5a470000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_UART1_CLK>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "uart1_lpcg_baud_clk", + "uart1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_1>; + }; + + uart2_lpcg: clock-controller@5a480000 { + reg = <0x5a480000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_UART2_CLK>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "uart2_lpcg_baud_clk", + "uart2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_2>; + }; + + uart3_lpcg: clock-controller@5a490000 { + reg = <0x5a490000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_UART3_CLK>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "uart3_lpcg_baud_clk", + "uart3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_3>; + }; + adma_i2c0: i2c@5a800000 { reg = <0x5a800000 0x4000>; interrupts = ; @@ -127,4 +205,48 @@ adma_subsys: bus@59000000 { power-domains = <&pd IMX_SC_R_I2C_3>; status = "disabled"; }; + + i2c0_lpcg: clock-controller@5ac00000 { + reg = <0x5ac00000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_I2C0_CLK>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "i2c0_lpcg_clk", + "i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_0>; + }; + + i2c1_lpcg: clock-controller@5ac10000 { + reg = <0x5ac10000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_I2C1_CLK>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "i2c1_lpcg_clk", + "i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_1>; + }; + + i2c2_lpcg: clock-controller@5ac20000 { + reg = <0x5ac20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_I2C2_CLK>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "i2c2_lpcg_clk", + "i2c2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_2>; + }; + + i2c3_lpcg: clock-controller@5ac30000 { + reg = <0x5ac30000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_I2C3_CLK>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "i2c3_lpcg_clk", + "i2c3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_3>; + }; };