@@ -284,6 +284,37 @@ int cmdq_pkt_write_s(struct cmdq_pkt *pkt, phys_addr_t addr, u16 reg_idx,
}
EXPORT_SYMBOL(cmdq_pkt_write_s);
+int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, dma_addr_t addr,
+ u32 value, u32 mask)
+{
+ struct cmdq_instruction inst = { {0} };
+ int err;
+ const u16 dst_reg_idx = CMDQ_SPR_TEMP;
+
+ err = cmdq_pkt_assign(pkt, dst_reg_idx, CMDQ_ADDR_HIGH(addr));
+ if (err < 0)
+ return err;
+
+ if (mask != U32_MAX) {
+ inst.op = CMDQ_CODE_MASK;
+ inst.mask = ~mask;
+ err = cmdq_pkt_append_command(pkt, inst);
+ if (err < 0)
+ return err;
+
+ inst.op = CMDQ_CODE_WRITE_S_MASK;
+ } else {
+ inst.op = CMDQ_CODE_WRITE_S;
+ }
+
+ inst.sop = dst_reg_idx;
+ inst.offset = CMDQ_ADDR_LOW(addr);
+ inst.value = value;
+
+ return cmdq_pkt_append_command(pkt, inst);
+}
+EXPORT_SYMBOL(cmdq_pkt_write_s_value);
+
int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
{
struct cmdq_instruction inst = { {0} };
@@ -128,6 +128,18 @@ int cmdq_pkt_read_s(struct cmdq_pkt *pkt, phys_addr_t addr, u16 reg_idx);
int cmdq_pkt_write_s(struct cmdq_pkt *pkt, phys_addr_t addr, u16 reg_idx,
u32 mask);
+/**
+ * cmdq_pkt_write_s() - append write_s command with mask to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @addr: the physical address of register or dma
+ * @value: the specified target value
+ * @mask: the specified target mask
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, dma_addr_t addr,
+ u32 value, u32 mask);
+
/**
* cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
* @pkt: the CMDQ packet
add write_s function in cmdq helper functions which writes a constant value to address with large dma access support. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> --- drivers/soc/mediatek/mtk-cmdq-helper.c | 31 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 12 ++++++++++ 2 files changed, 43 insertions(+)