diff mbox series

arm64: cpu_errata: Add Hisilicon TSV110 to spectre-v2 safe list

Message ID 1576833430-11839-1-git-send-email-guohanjun@huawei.com (mailing list archive)
State Mainlined
Commit aa638cfe3e7358122a15cb1d295b622aae69e006
Headers show
Series arm64: cpu_errata: Add Hisilicon TSV110 to spectre-v2 safe list | expand

Commit Message

Hanjun Guo Dec. 20, 2019, 9:17 a.m. UTC 
From: Wei Li <liwei391@huawei.com>

HiSilicon Taishan v110 CPUs didn't implement CSV2 field of the
ID_AA64PFR0_EL1, but spectre-v2 is mitigated by hardware, so
whitelist the MIDR in the safe list.

Signed-off-by: Wei Li <liwei391@huawei.com>
[hanjun: re-write the commit log]
Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
---
 arch/arm64/kernel/cpu_errata.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Catalin Marinas Dec. 20, 2019, 5:57 p.m. UTC | #1 
On Fri, Dec 20, 2019 at 05:17:10PM +0800, Hanjun Guo wrote:
> From: Wei Li <liwei391@huawei.com>
> 
> HiSilicon Taishan v110 CPUs didn't implement CSV2 field of the
> ID_AA64PFR0_EL1, but spectre-v2 is mitigated by hardware, so
> whitelist the MIDR in the safe list.
> 
> Signed-off-by: Wei Li <liwei391@huawei.com>
> [hanjun: re-write the commit log]
> Signed-off-by: Hanjun Guo <guohanjun@huawei.com>

Queued for 5.5. Thanks.
diff mbox series

Patch

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 6a09ca7..85f4bec 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -547,6 +547,7 @@  int get_spectre_v2_workaround_state(void)
 	MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 	MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 	MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
+	MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 	{ /* sentinel */ }
 };