| Message ID | 1583928220724.65021@wiedemann-group.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | d5b2b22558f1a265ea8e88e5a54fc61ae7da3355 |
| Headers | show |
| Series | clk: imx: imx6ul: change flexcan clock to support CiA bitrates | expand |
On Wed, Mar 11, 2020 at 12:03:40PM +0000, Waibel Georg wrote: > Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the > flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock > frequency from 30MHz to 40MHz which allows to support all bitrates recommended But code changes IMX6UL_CLK_PLL3_60M to IMX6UL_CLK_PLL3_80M? Or IMX6UL_CLK_CAN_SEL is different from CAN_CLK_ROOT in the context? Shawn > by CiA. > > Background: > CAN in Automation document 102 (CiA102) recommends the CAN bitrates 10, 20, 50, > 125, 250, 500, 800 and 1000kbit/s. > > With the flexcan serial clock at 30MHz (original value) setting some common > bitrates ("ip link set canX type can bitrate <bitrate>") gives the following > results: > requested value / actually set value > 5000: bitrate 5000 sample-point 0.708 > 10000: bitrate 10000 sample-point 0.866 > 20000: bitrate 20000 sample-point 0.866 > 40000: bitrate 40000 sample-point 0.866 > 50000: bitrate 50000 sample-point 0.866 > 80000: bitrate 80000 sample-point 0.866 > 100000: bitrate 100000 sample-point 0.866 > 125000: bitrate 125000 sample-point 0.875 > 250000: bitrate 250000 sample-point 0.866 > 400000: bitrate 400000 sample-point 0.866 > 500000: bitrate 500000 sample-point 0.866 > 666666: bitrate 666666 sample-point 0.800 > 800000: bitrate 789473 sample-point 0.789 !!!bitrate error 1.3% > 1000000: bitrate 1000000 sample-point 0.733 > > With the flexcan serial clock at 40MHz (new value) we get this: > 5000: no more possible > 10000: bitrate 10000 sample-point 0.875 > 20000: bitrate 20000 sample-point 0.875 > 40000: bitrate 40000 sample-point 0.850 > 50000: bitrate 50000 sample-point 0.875 > 80000: bitrate 80000 sample-point 0.850 > 100000: bitrate 100000 sample-point 0.875 > 125000: bitrate 125000 sample-point 0.875 > 250000: bitrate 250000 sample-point 0.875 > 400000: bitrate 400000 sample-point 0.850 > 500000: bitrate 500000 sample-point 0.875 > 666666: bitrate 666666 sample-point 0.800 > 800000: bitrate 800000 sample-point 0.800 > 1000000: bitrate 1000000 sample-point 0.750 > > A drawback of the modification is that 5kbit/s is no more supported. > > Setting the flexcan serial clock to 60MHz or 80MHz would produce similar > results but with losing even more bitrates at the lower end. > > Changing the flexcan serial clock to 40MHz might apply for other SoCs > using the flaxcan module as well (e.g. imx6q/d/s..). But since I don't > have such hardware to test I did not add this to the patch. > > Signed-off-by: Georg Waibel <georg.waibel@wiedemann-group.de> > --- > drivers/clk/imx/clk-imx6ul.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c > index dafc8806b03e..5dbb6a937732 100644 > --- a/drivers/clk/imx/clk-imx6ul.c > +++ b/drivers/clk/imx/clk-imx6ul.c > @@ -503,7 +503,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) > clk_prepare_enable(hws[IMX6UL_CLK_USBPHY2_GATE]->clk); > } > > - clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_60M]->clk); > + clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_80M]->clk); > if (clk_on_imx6ul()) > clk_set_parent(hws[IMX6UL_CLK_SIM_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_USB_OTG]->clk); > else if (clk_on_imx6ull()) > -- > 2.17.1 > > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Mon, 16 Mar 2020 at 02:30, Shawn Guo <shawnguo@kernel.org> wrote: > On Wed, Mar 11, 2020 at 12:03:40PM +0000, Waibel Georg wrote: > > Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the > > flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock > > frequency from 30MHz to 40MHz which allows to support all bitrates recommended > > But code changes IMX6UL_CLK_PLL3_60M to IMX6UL_CLK_PLL3_80M? Or > IMX6UL_CLK_CAN_SEL is different from CAN_CLK_ROOT in the context? Correct. The patch sets CAN_CLK_SEL to 80MHZ. There is a post-divider CAN_CLK_PODF which is set to /2 by default which makes the 40MHz
On Mon, 16 Mar 2020 at 02:30, Shawn Guo <shawnguo@kernel.org> wrote: > On Wed, Mar 11, 2020 at 12:03:40PM +0000, Waibel Georg wrote: > > Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the > > flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock > > frequency from 30MHz to 40MHz which allows to support all bitrates recommended > > But code changes IMX6UL_CLK_PLL3_60M to IMX6UL_CLK_PLL3_80M? Or > IMX6UL_CLK_CAN_SEL is different from CAN_CLK_ROOT in the context? Correct. The patch sets CAN_CLK_SEL to 80MHZ. There is a post-divider CAN_CLK_PODF which is set to /2 by default which makes the 40MHz CAN_CLK_ROOT. Regards Georg
On Mon, Mar 16, 2020 at 09:58:28AM +0000, Waibel Georg wrote: > On Mon, 16 Mar 2020 at 02:30, Shawn Guo <shawnguo@kernel.org> wrote: > > On Wed, Mar 11, 2020 at 12:03:40PM +0000, Waibel Georg wrote: > > > Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the > > > flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock > > > frequency from 30MHz to 40MHz which allows to support all bitrates recommended > > > > But code changes IMX6UL_CLK_PLL3_60M to IMX6UL_CLK_PLL3_80M? Or > > IMX6UL_CLK_CAN_SEL is different from CAN_CLK_ROOT in the context? > > Correct. The patch sets CAN_CLK_SEL to 80MHZ. There is a post-divider > CAN_CLK_PODF which is set to /2 by default which makes the 40MHz > CAN_CLK_ROOT. Could you add this into commit log to make it clear? Shawn
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index dafc8806b03e..5dbb6a937732 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -503,7 +503,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clk_prepare_enable(hws[IMX6UL_CLK_USBPHY2_GATE]->clk); } - clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_60M]->clk); + clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_80M]->clk); if (clk_on_imx6ul()) clk_set_parent(hws[IMX6UL_CLK_SIM_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_USB_OTG]->clk); else if (clk_on_imx6ull())
Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock frequency from 30MHz to 40MHz which allows to support all bitrates recommended by CiA. Background: CAN in Automation document 102 (CiA102) recommends the CAN bitrates 10, 20, 50, 125, 250, 500, 800 and 1000kbit/s. With the flexcan serial clock at 30MHz (original value) setting some common bitrates ("ip link set canX type can bitrate <bitrate>") gives the following results: requested value / actually set value 5000: bitrate 5000 sample-point 0.708 10000: bitrate 10000 sample-point 0.866 20000: bitrate 20000 sample-point 0.866 40000: bitrate 40000 sample-point 0.866 50000: bitrate 50000 sample-point 0.866 80000: bitrate 80000 sample-point 0.866 100000: bitrate 100000 sample-point 0.866 125000: bitrate 125000 sample-point 0.875 250000: bitrate 250000 sample-point 0.866 400000: bitrate 400000 sample-point 0.866 500000: bitrate 500000 sample-point 0.866 666666: bitrate 666666 sample-point 0.800 800000: bitrate 789473 sample-point 0.789 !!!bitrate error 1.3% 1000000: bitrate 1000000 sample-point 0.733 With the flexcan serial clock at 40MHz (new value) we get this: 5000: no more possible 10000: bitrate 10000 sample-point 0.875 20000: bitrate 20000 sample-point 0.875 40000: bitrate 40000 sample-point 0.850 50000: bitrate 50000 sample-point 0.875 80000: bitrate 80000 sample-point 0.850 100000: bitrate 100000 sample-point 0.875 125000: bitrate 125000 sample-point 0.875 250000: bitrate 250000 sample-point 0.875 400000: bitrate 400000 sample-point 0.850 500000: bitrate 500000 sample-point 0.875 666666: bitrate 666666 sample-point 0.800 800000: bitrate 800000 sample-point 0.800 1000000: bitrate 1000000 sample-point 0.750 A drawback of the modification is that 5kbit/s is no more supported. Setting the flexcan serial clock to 60MHz or 80MHz would produce similar results but with losing even more bitrates at the lower end. Changing the flexcan serial clock to 40MHz might apply for other SoCs using the flaxcan module as well (e.g. imx6q/d/s..). But since I don't have such hardware to test I did not add this to the patch. Signed-off-by: Georg Waibel <georg.waibel@wiedemann-group.de> --- drivers/clk/imx/clk-imx6ul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)