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X-Microsoft-Antispam-Message-Info: PBOGHYBxUL8FGXL4WX07nhT3dTcUOhq+LnZlVm6P1B6S+KisnV4BShZFAnNJZOzzHEyfC3HPP6LtcUQwPRxCMQB48DW71CLASy1yFweCE8edum/kW57vmHwPeyW5Rj0wnS1UYWfPtPbGXufSPCCyl5Xy7K75dQSrEKxSlz7j/FoLM73nJ+MpfIFD1ppKYzq587hu1BoaTfvqZ3wYKPPmzknLxfYMLbLJ5v8G5xTSP359EL36hXxzgRfSFShkax2PdoilOnDurIqe9gpx/JADdZjXn+pM6ta5ZPYoXs0jNaShx0Gi29XfFmXx7khh9zdbOKpoESjtGOce7MKC/AtcykoSSobjbUDbLytU3O9ZXMaPczxuEtn3dlZjaLqLSJcHUV4J720wxoa6QjOEs0CGQKq/G5dAi/uiNZwxWuJmw7VMqOLlkv5Rao14SSw6OMIBfmkB1gMnDD9ZpsocKWNmAXHo8lagMjANDeaDrJiErbycffjuzvKuHVe1U1edaET9 X-MS-Exchange-AntiSpam-MessageData: dyNYyDdcFUHdCzl5QrCI0vQJxM7+mEus1foNhA2vkkf3df8Z3fKTULVIpsoWNkmDraT7yFZFMEICvwt1qn3dA4ilM3fpyN+e5TGxCDlLLhIl2oqCd4Am3mq1MBh6Ew21/Qit2+uJ4GE7OyhlEddJng== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7d5423a9-3aff-444e-5376-08d7c6672564 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2020 09:24:20.9346 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NLvHly9FcFqfzUeqV9hYz7/2lFvU9UzjJjqrEBPEXCXV8/HadndJq2jhb09zbsPf1ypchOzP3XYllzfy4kDveA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5588 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200312_022424_999645_0F632BF8 X-CRM114-Status: GOOD ( 11.67 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.7.45 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [40.107.7.45 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Peng Fan , abel.vesa@nxp.com, Anson.Huang@nxp.com, ard.biesheuvel@linaro.org, festevam@gmail.com, linux-kernel@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, git@andred.net, leonard.crestez@nxp.com, info@metux.net, allison@lohutok.net Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Peng Fan The soc device register code will be moved to drivers/soc/imx/, the code needs the cpu type definitions. So let's move the cpu type definitions to a header. Signed-off-by: Peng Fan --- arch/arm/mach-imx/mxc.h | 22 +--------------------- include/soc/imx/cpu.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 21 deletions(-) create mode 100644 include/soc/imx/cpu.h diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 2bfd2d59b4a6..fe2d0f5abfcc 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -8,35 +8,15 @@ #define __ASM_ARCH_MXC_H__ #include +#include #ifndef __ASM_ARCH_MXC_HARDWARE_H__ #error "Do not include directly." #endif -#define MXC_CPU_MX1 1 -#define MXC_CPU_MX21 21 -#define MXC_CPU_MX25 25 -#define MXC_CPU_MX27 27 -#define MXC_CPU_MX31 31 -#define MXC_CPU_MX35 35 -#define MXC_CPU_MX51 51 -#define MXC_CPU_MX53 53 -#define MXC_CPU_IMX6SL 0x60 -#define MXC_CPU_IMX6DL 0x61 -#define MXC_CPU_IMX6SX 0x62 -#define MXC_CPU_IMX6Q 0x63 -#define MXC_CPU_IMX6UL 0x64 -#define MXC_CPU_IMX6ULL 0x65 -/* virtual cpu id for i.mx6ulz */ -#define MXC_CPU_IMX6ULZ 0x6b -#define MXC_CPU_IMX6SLL 0x67 -#define MXC_CPU_IMX7D 0x72 -#define MXC_CPU_IMX7ULP 0xff - #define IMX_DDR_TYPE_LPDDR2 1 #ifndef __ASSEMBLY__ -extern unsigned int __mxc_cpu_type; #ifdef CONFIG_SOC_IMX6SL static inline bool cpu_is_imx6sl(void) diff --git a/include/soc/imx/cpu.h b/include/soc/imx/cpu.h new file mode 100644 index 000000000000..0669fc08a501 --- /dev/null +++ b/include/soc/imx/cpu.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __IMX_CPU_H__ +#define __IMX_CPU_H__ + +#define MXC_CPU_MX1 1 +#define MXC_CPU_MX21 21 +#define MXC_CPU_MX25 25 +#define MXC_CPU_MX27 27 +#define MXC_CPU_MX31 31 +#define MXC_CPU_MX35 35 +#define MXC_CPU_MX51 51 +#define MXC_CPU_MX53 53 +#define MXC_CPU_IMX6SL 0x60 +#define MXC_CPU_IMX6DL 0x61 +#define MXC_CPU_IMX6SX 0x62 +#define MXC_CPU_IMX6Q 0x63 +#define MXC_CPU_IMX6UL 0x64 +#define MXC_CPU_IMX6ULL 0x65 +/* virtual cpu id for i.mx6ulz */ +#define MXC_CPU_IMX6ULZ 0x6b +#define MXC_CPU_IMX6SLL 0x67 +#define MXC_CPU_IMX7D 0x72 +#define MXC_CPU_IMX7ULP 0xff + +#ifndef __ASSEMBLY__ +extern unsigned int __mxc_cpu_type; +#endif + +#endif