From patchwork Wed Jul 1 05:25:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 11635395 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1E6EB618 for ; Wed, 1 Jul 2020 06:31:00 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E7FC320663 for ; Wed, 1 Jul 2020 06:30:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="H2/EX417" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E7FC320663 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Owner; bh=jCKbQMqjhkwCOENjTdoeQW+MIv1l2614cWfncX6/H1g=; b=H2/EX417+LLjbDq4rBpSFS8LVZ IcMtecjfdO1HRhW7psSCVJU+G/yrDD2duLBcDM6nl3Ldd2YfpY+Vm3BlQjuIHVkNdZCAbxKrUpm3E btU8II7eZK1hvSlzCV5fUtfaD/hxvbgMYnqJPALbjNImkx07EjiU+qNj/Q+ajD9YTWD22W6lJOoQ3 gFs+S9rH/uZjiqqR3m7pB8KLf2rmee9Og/c0nECDZlRAbsZnFNi3jLvU++5OAKoj5lUknTQMLxxL7 kDIrDCQduPSUWE1DR+YV+B6MMmXqhJBMJS/k0rHKNT6YfpT7C2EB8wmTLAwpyzvk6iahy1gt3QpnD p/HL1KzA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqWFj-0004A4-P6; Wed, 01 Jul 2020 06:29:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqVG1-0006GF-HX for linux-arm-kernel@lists.infradead.org; Wed, 01 Jul 2020 05:26:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2346730E; Tue, 30 Jun 2020 22:26:04 -0700 (PDT) Received: from p8cg001049571a15.arm.com (unknown [10.163.84.122]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D88273F73C; Tue, 30 Jun 2020 22:25:58 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V2] arm64/cpufeature: Validate feature bits spacing in arm64_ftr_regs[] Date: Wed, 1 Jul 2020 10:55:40 +0530 Message-Id: <1593581140-4339-1-git-send-email-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200701_012605_720382_4738138E X-CRM114-Status: GOOD ( 14.93 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [217.140.110.172 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Suzuki K Poulose , Catalin Marinas , Anshuman Khandual , linux-kernel@vger.kernel.org, Mark Brown , Will Deacon MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org arm64_feature_bits for a register in arm64_ftr_regs[] are in a descending order as per their shift values. Validate that these features bits are defined correctly and do not overlap with each other. This check protects against any inadvertent erroneous changes to the register definitions. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Mark Brown Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Suzuki K Poulose --- Applies on 5.8-rc3. Changes in V2: - Replaced WARN_ON() with WARN() dropping the conditional block per Suzuki Changes in V1: (https://patchwork.kernel.org/patch/11606285/) arch/arm64/kernel/cpufeature.c | 45 +++++++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9f63053a63a9..7bd7e6f936a5 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -697,11 +697,50 @@ static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, static void __init sort_ftr_regs(void) { - int i; + const struct arm64_ftr_reg *ftr_reg; + const struct arm64_ftr_bits *ftr_bits; + unsigned int i, j, width, shift, prev_shift; + + for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { + /* + * Features here must be sorted in descending order with respect + * to their shift values and should not overlap with each other. + */ + ftr_reg = arm64_ftr_regs[i].reg; + for (ftr_bits = ftr_reg->ftr_bits, j = 0; + ftr_bits->width != 0; ftr_bits++, j++) { + WARN((ftr_bits->shift + ftr_bits->width) > 64, + "%s has invalid feature at shift %d\n", + ftr_reg->name, ftr_bits->shift); + + /* + * Skip the first feature. There is nothing to + * compare against for now. + */ + if (j == 0) + continue; + + prev_shift = ftr_reg->ftr_bits[j - 1].shift; + width = ftr_reg->ftr_bits[j].width; + shift = ftr_reg->ftr_bits[j].shift; + WARN(prev_shift < (shift + width), + "%s has feature overlap at shift %d\n", + ftr_reg->name, ftr_bits->shift); + } - /* Check that the array is sorted so that we can do the binary search */ - for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) + /* + * Skip the first register. There is nothing to + * compare against for now. + */ + if (i == 0) + continue; + /* + * Registers here must be sorted in ascending order with respect + * to sys_id for subsequent binary search in get_arm64_ftr_reg() + * to work correctly. + */ BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); + } } /*