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Wed, 01 Jul 2020 23:08:14 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 2 Jul 2020 00:06:09 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 2 Jul 2020 15:06:06 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 2 Jul 2020 15:06:08 +0800 From: EastL Lee To: Sean Wang Subject: [PATCH v6 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings Date: Thu, 2 Jul 2020 15:06:01 +0800 Message-ID: <1593673564-4425-2-git-send-email-EastL.Lee@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1593673564-4425-1-git-send-email-EastL.Lee@mediatek.com> References: <1593673564-4425-1-git-send-email-EastL.Lee@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: F3A085BAD89C115B095C1B7865FA2C326AC77083018D7895F5C7BDECC91F38FB2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200702_030822_894745_CC84C257 X-CRM114-Status: GOOD ( 12.20 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, cc.hwang@mediatek.com, wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, EastL Lee , dmaengine@vger.kernel.org, vkoul@kernel.org, robh+dt@kernel.org, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Document the devicetree bindings for MediaTek Command-Queue DMA controller which could be found on MT6779 SoC or other similar Mediatek SoCs. Signed-off-by: EastL Lee --- .../devicetree/bindings/dma/mtk-cqdma.yaml | 113 +++++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml new file mode 100644 index 0000000..83ed742 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Command-Queue DMA controller Device Tree Binding + +maintainers: + - EastL Lee + +description: + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC + is dedicated to memory-to-memory transfer through queue based + descriptor management. + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + "#dma-cells": + minimum: 1 + maximum: 255 + description: + Used to provide DMA controller specific information. + + compatible: + oneOf: + - const: mediatek,mt6765-cqdma + - const: mediatek,mt6779-cqdma + + reg: + minItems: 1 + maxItems: 5 + description: + A base address of MediaTek Command-Queue DMA controller, + a channel will have a set of base address. + + interrupts: + minItems: 1 + maxItems: 5 + description: + A interrupt number of MediaTek Command-Queue DMA controller, + one interrupt number per dma-channels. + + clocks: + maxItems: 1 + + clock-names: + const: cqdma + + dma-channel-mask: + $ref: /schemas/types.yaml#definitions/uint32 + description: + For DMA capability, We will know the addressing capability of + MediaTek Command-Queue DMA controller through dma-channel-mask. + items: + minItems: 1 + maxItems: 63 + + dma-channels: + $ref: /schemas/types.yaml#definitions/uint32 + description: + Number of DMA channels supported by MediaTek Command-Queue DMA + controller, support up to five. + items: + minItems: 1 + maxItems: 5 + + dma-requests: + $ref: /schemas/types.yaml#definitions/uint32 + description: + Number of DMA request (virtual channel) supported by MediaTek + Command-Queue DMA controller, support up to 32. + items: + minItems: 1 + maxItems: 32 + +required: + - "#dma-cells" + - compatible + - reg + - interrupts + - clocks + - clock-names + - dma-channel-mask + - dma-channels + - dma-requests + +additionalProperties: false + +examples: + - | + #include + #include + #include + cqdma: dma-controller@10212000 { + compatible = "mediatek,mt6779-cqdma"; + reg = <0x10212000 0x80>, + <0x10212080 0x80>, + <0x10212100 0x80>; + interrupts = , + , + ; + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>; + clock-names = "cqdma"; + dma-channel-mask = <63>; + dma-channels = <3>; + dma-requests = <32>; + #dma-cells = <1>; + }; + +...