diff mbox series

[04/19] clk: at91: sam9x60-pll: use frac when computing pll frequency

Message ID 1594812267-6697-5-git-send-email-claudiu.beznea@microchip.com (mailing list archive)
State New, archived
Headers show
Series clk: at91: add sama7g5 clock support | expand

Commit Message

Claudiu Beznea July 15, 2020, 11:24 a.m. UTC 
According to datasheet the PLL frequency is computed using the following
formula: parent_rate * (mul + 1 + frac/2^22)/(div + 1). Use this
formula.

Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/clk/at91/clk-sam9x60-pll.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index 3522eae2edd6..d3152c0afcbf 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -152,7 +152,8 @@  static unsigned long sam9x60_pll_recalc_rate(struct clk_hw *hw,
 {
 	struct sam9x60_pll *pll = to_sam9x60_pll(hw);
 
-	return (parent_rate * (pll->mul + 1)) / (pll->div + 1);
+	return DIV_ROUND_CLOSEST_ULL((parent_rate * (pll->mul + 1) +
+		((u64)parent_rate * pll->frac >> 22)), (pll->div + 1));
 }
 
 static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,