diff mbox series

[07/19] clk: at91: sam9x60-pll: use frac when setting frequency

Message ID 1594812267-6697-8-git-send-email-claudiu.beznea@microchip.com (mailing list archive)
State New, archived
Headers show
Series clk: at91: add sama7g5 clock support | expand

Commit Message

Claudiu Beznea July 15, 2020, 11:24 a.m. UTC
In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
the fractional part of PLL wasn't set on registers but it was
calculated and taken into account for determining div and mul
(see sam9x60_pll_get_best_div_mul()).

Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/clk/at91/clk-sam9x60-pll.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Alexandre Belloni July 17, 2020, 9:12 a.m. UTC | #1
On 15/07/2020 14:24:15+0300, Claudiu Beznea wrote:
> In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
> the fractional part of PLL wasn't set on registers but it was
> calculated and taken into account for determining div and mul
> (see sam9x60_pll_get_best_div_mul()).
> 

I think this becomes an issue only once 4/19 is applied so you should
probably squash those two together.

> Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  drivers/clk/at91/clk-sam9x60-pll.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index 00f2afd6e9b6..13e15bd48770 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -16,6 +16,7 @@
>  
>  #define	PMC_PLL_CTRL0_DIV_MSK	GENMASK(7, 0)
>  #define	PMC_PLL_CTRL1_MUL_MSK	GENMASK(31, 24)
> +#define	PMC_PLL_CTRL1_FRACR_MSK	GENMASK(21, 0)
>  
>  #define PLL_DIV_MAX		(FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
>  #define UPLL_DIV		2
> @@ -55,7 +56,7 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
>  	unsigned long flags;
>  	u8 div;
>  	u16 mul;
> -	u32 val;
> +	u32 val, frac;
>  
>  	spin_lock_irqsave(pll->lock, flags);
>  	regmap_write(regmap, AT91_PMC_PLL_UPDT, pll->id);
> @@ -65,9 +66,10 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
>  
>  	regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
>  	mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
> +	frac = FIELD_GET(PMC_PLL_CTRL1_FRACR_MSK, val);
>  
>  	if (sam9x60_pll_ready(regmap, pll->id) &&
> -	    (div == pll->div && mul == pll->mul)) {
> +	    (div == pll->div && mul == pll->mul && frac == pll->frac)) {
>  		spin_unlock_irqrestore(pll->lock, flags);
>  		return 0;
>  	}
> @@ -80,7 +82,8 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
>  	regmap_write(regmap, AT91_PMC_PLL_ACR, val);
>  
>  	regmap_write(regmap, AT91_PMC_PLL_CTRL1,
> -		     FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul));
> +		     FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul) |
> +		     FIELD_PREP(PMC_PLL_CTRL1_FRACR_MSK, pll->frac));
>  
>  	if (pll->characteristics->upll) {
>  		/* Enable the UTMI internal bandgap */
> -- 
> 2.7.4
>
Claudiu Beznea July 20, 2020, 10:34 a.m. UTC | #2
On 17.07.2020 12:12, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 15/07/2020 14:24:15+0300, Claudiu Beznea wrote:
>> In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
>> the fractional part of PLL wasn't set on registers but it was
>> calculated and taken into account for determining div and mul
>> (see sam9x60_pll_get_best_div_mul()).
>>
> 
> I think this becomes an issue only once 4/19 is applied so you should
> probably squash those two together.

I kept it separate as I was thinking about the scenario where
the bootloaders set up the frequency using also fractional part.

But at the same time I was thinking about squashing them together.
Now that there is also someone thinking about having them
together (you) I will squash them.

Thank you,
Claudiu Beznea

> 
>> Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>>  drivers/clk/at91/clk-sam9x60-pll.c | 9 ++++++---
>>  1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
>> index 00f2afd6e9b6..13e15bd48770 100644
>> --- a/drivers/clk/at91/clk-sam9x60-pll.c
>> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
>> @@ -16,6 +16,7 @@
>>
>>  #define      PMC_PLL_CTRL0_DIV_MSK   GENMASK(7, 0)
>>  #define      PMC_PLL_CTRL1_MUL_MSK   GENMASK(31, 24)
>> +#define      PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
>>
>>  #define PLL_DIV_MAX          (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
>>  #define UPLL_DIV             2
>> @@ -55,7 +56,7 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
>>       unsigned long flags;
>>       u8 div;
>>       u16 mul;
>> -     u32 val;
>> +     u32 val, frac;
>>
>>       spin_lock_irqsave(pll->lock, flags);
>>       regmap_write(regmap, AT91_PMC_PLL_UPDT, pll->id);
>> @@ -65,9 +66,10 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
>>
>>       regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
>>       mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
>> +     frac = FIELD_GET(PMC_PLL_CTRL1_FRACR_MSK, val);
>>
>>       if (sam9x60_pll_ready(regmap, pll->id) &&
>> -         (div == pll->div && mul == pll->mul)) {
>> +         (div == pll->div && mul == pll->mul && frac == pll->frac)) {
>>               spin_unlock_irqrestore(pll->lock, flags);
>>               return 0;
>>       }
>> @@ -80,7 +82,8 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
>>       regmap_write(regmap, AT91_PMC_PLL_ACR, val);
>>
>>       regmap_write(regmap, AT91_PMC_PLL_CTRL1,
>> -                  FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul));
>> +                  FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul) |
>> +                  FIELD_PREP(PMC_PLL_CTRL1_FRACR_MSK, pll->frac));
>>
>>       if (pll->characteristics->upll) {
>>               /* Enable the UTMI internal bandgap */
>> --
>> 2.7.4
>>
> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>
diff mbox series

Patch

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index 00f2afd6e9b6..13e15bd48770 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -16,6 +16,7 @@ 
 
 #define	PMC_PLL_CTRL0_DIV_MSK	GENMASK(7, 0)
 #define	PMC_PLL_CTRL1_MUL_MSK	GENMASK(31, 24)
+#define	PMC_PLL_CTRL1_FRACR_MSK	GENMASK(21, 0)
 
 #define PLL_DIV_MAX		(FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
 #define UPLL_DIV		2
@@ -55,7 +56,7 @@  static int sam9x60_pll_prepare(struct clk_hw *hw)
 	unsigned long flags;
 	u8 div;
 	u16 mul;
-	u32 val;
+	u32 val, frac;
 
 	spin_lock_irqsave(pll->lock, flags);
 	regmap_write(regmap, AT91_PMC_PLL_UPDT, pll->id);
@@ -65,9 +66,10 @@  static int sam9x60_pll_prepare(struct clk_hw *hw)
 
 	regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
 	mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
+	frac = FIELD_GET(PMC_PLL_CTRL1_FRACR_MSK, val);
 
 	if (sam9x60_pll_ready(regmap, pll->id) &&
-	    (div == pll->div && mul == pll->mul)) {
+	    (div == pll->div && mul == pll->mul && frac == pll->frac)) {
 		spin_unlock_irqrestore(pll->lock, flags);
 		return 0;
 	}
@@ -80,7 +82,8 @@  static int sam9x60_pll_prepare(struct clk_hw *hw)
 	regmap_write(regmap, AT91_PMC_PLL_ACR, val);
 
 	regmap_write(regmap, AT91_PMC_PLL_CTRL1,
-		     FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul));
+		     FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul) |
+		     FIELD_PREP(PMC_PLL_CTRL1_FRACR_MSK, pll->frac));
 
 	if (pll->characteristics->upll) {
 		/* Enable the UTMI internal bandgap */