diff mbox series

[3/3] arm64: dts: Add power controller device node of MT8192

Message ID 1599201895-11013-4-git-send-email-weiyi.lu@mediatek.com
State New, archived
Headers show
Series Mediatek MT8192 scpsys support | expand

Commit Message

Weiyi Lu Sept. 4, 2020, 6:44 a.m. UTC
Add power controller node for MT8192.
In scpsys node, it contains clocks and regmapping of
infracfg for bus protection.
And list all the power domains of MT8192 under scpsys node
to show the dependency between each other through hierarchical
structure.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 148 +++++++++++++++++++++++++++++++
 1 file changed, 148 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index b3fab4f..be90137 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@ 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/power/mt8192-power.h>
 
 / {
 	compatible = "mediatek,mt8192";
@@ -257,6 +258,153 @@ 
 			#interrupt-cells = <2>;
 		};
 
+		scpsys: power-controller@10006000 {
+			compatible = "mediatek,mt8192-scpsys", "syscon";
+			reg = <0 0x10006000 0 0x1000>;
+			clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+				 <&infracfg CLK_INFRA_AUDIO_26M_B>,
+				 <&infracfg CLK_INFRA_AUDIO>,
+				 <&infracfg CLK_INFRA_PMIC_CONN>,
+				 <&topckgen CLK_TOP_MFG_PLL_SEL>,
+				 <&topckgen CLK_TOP_DISP_SEL>,
+				 <&infracfg CLK_INFRA_DEVICE_APC_SYNC>,
+				 <&topckgen CLK_TOP_IPE_SEL>,
+				 <&topckgen CLK_TOP_IMG1_SEL>,
+				 <&topckgen CLK_TOP_IMG2_SEL>,
+				 <&topckgen CLK_TOP_MDP_SEL>,
+				 <&topckgen CLK_TOP_VENC_SEL>,
+				 <&topckgen CLK_TOP_VDEC_SEL>,
+				 <&topckgen CLK_TOP_CAM_SEL>;
+			clock-names = "audio", "audio1", "audio2", "conn", "mfg",
+				      "disp", "disp1", "ipe", "isp", "isp1",
+				      "mdp", "venc", "vdec", "cam";
+			infracfg = <&infracfg>;
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			audio@MT8192_POWER_DOMAIN_AUDIO {
+				reg = <MT8192_POWER_DOMAIN_AUDIO>;
+			};
+
+			conn@MT8192_POWER_DOMAIN_CONN {
+				reg = <MT8192_POWER_DOMAIN_CONN>;
+			};
+
+			mfg@MT8192_POWER_DOMAIN_MFG0 {
+				reg = <MT8192_POWER_DOMAIN_MFG0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mfg1@MT8192_POWER_DOMAIN_MFG1 {
+					reg = <MT8192_POWER_DOMAIN_MFG1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					mfg2@MT8192_POWER_DOMAIN_MFG2 {
+						reg = <MT8192_POWER_DOMAIN_MFG2>;
+					};
+
+					mfg3@MT8192_POWER_DOMAIN_MFG3 {
+						reg = <MT8192_POWER_DOMAIN_MFG3>;
+					};
+
+					mfg4@MT8192_POWER_DOMAIN_MFG4 {
+						reg = <MT8192_POWER_DOMAIN_MFG4>;
+					};
+
+					mfg5@MT8192_POWER_DOMAIN_MFG5 {
+						reg = <MT8192_POWER_DOMAIN_MFG5>;
+					};
+
+					mfg6@MT8192_POWER_DOMAIN_MFG6 {
+						reg = <MT8192_POWER_DOMAIN_MFG6>;
+					};
+				};
+			};
+
+			disp@MT8192_POWER_DOMAIN_DISP {
+				reg = <MT8192_POWER_DOMAIN_DISP>;
+				clocks = <&mmsys CLK_MM_SMI_INFRA>,
+					 <&mmsys CLK_MM_SMI_COMMON>,
+					 <&mmsys CLK_MM_SMI_GALS>,
+					 <&mmsys CLK_MM_SMI_IOMMU>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ipe@MT8192_POWER_DOMAIN_IPE {
+					reg = <MT8192_POWER_DOMAIN_IPE>;
+					clocks = <&ipesys CLK_IPE_LARB19>,
+						 <&ipesys CLK_IPE_LARB20>,
+						 <&ipesys CLK_IPE_SMI_SUBCOM>,
+						 <&ipesys CLK_IPE_GALS>;
+				};
+
+				isp@MT8192_POWER_DOMAIN_ISP {
+					reg = <MT8192_POWER_DOMAIN_ISP>;
+					clocks = <&imgsys CLK_IMG_LARB9>,
+						 <&imgsys CLK_IMG_GALS>;
+				};
+
+				isp2@MT8192_POWER_DOMAIN_ISP2 {
+					reg = <MT8192_POWER_DOMAIN_ISP2>;
+					clocks = <&imgsys2 CLK_IMG2_LARB11>,
+						 <&imgsys2 CLK_IMG2_GALS>;
+				};
+
+				mdp@MT8192_POWER_DOMAIN_MDP {
+					reg = <MT8192_POWER_DOMAIN_MDP>;
+					clocks = <&mdpsys CLK_MDP_SMI0>;
+				};
+
+				venc@MT8192_POWER_DOMAIN_VENC {
+					reg = <MT8192_POWER_DOMAIN_VENC>;
+					clocks = <&vencsys CLK_VENC_SET1_VENC>;
+				};
+
+				vdec@MT8192_POWER_DOMAIN_VDEC {
+					reg = <MT8192_POWER_DOMAIN_VDEC>;
+					clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+						 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+						 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					vdec2@MT8192_POWER_DOMAIN_VDEC2 {
+						reg = <MT8192_POWER_DOMAIN_VDEC2>;
+						clocks = <&vdecsys CLK_VDEC_VDEC>,
+							 <&vdecsys CLK_VDEC_LAT>,
+							 <&vdecsys CLK_VDEC_LARB1>;
+					};
+				};
+
+				cam@MT8192_POWER_DOMAIN_CAM {
+					reg = <MT8192_POWER_DOMAIN_CAM>;
+					clocks = <&camsys CLK_CAM_LARB13>,
+						 <&camsys CLK_CAM_LARB14>,
+						 <&camsys CLK_CAM_CCU_GALS>,
+						 <&camsys CLK_CAM_CAM2MM_GALS>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					cam_rawa@MT8192_POWER_DOMAIN_CAM_RAWA {
+						reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
+						clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+					};
+
+					cam_rawb@MT8192_POWER_DOMAIN_CAM_RAWB {
+						reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
+						clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+					};
+
+					cam_rawc@MT8192_POWER_DOMAIN_CAM_RAWC {
+						reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
+						clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
+					};
+				};
+			};
+		};
+
 		watchdog: watchdog@10007000 {
 			compatible = "mediatek,mt8192-wdt";
 			reg = <0 0x10007000 0 0x100>;