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}; -&pcie { +&pcie1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index ff19ec4..6a2c091 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -1,8 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Device Tree Include file for Freescale Layerscape-1012A family SoC. + * Device Tree Include file for NXP Layerscape-1012A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019-2020 NXP * */ @@ -489,7 +490,7 @@ interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; }; - pcie: pcie@3400000 { + pcie1: pcie@3400000 { compatible = "fsl,ls1012a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */