From patchwork Mon Sep 21 09:50:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "liuqi (BA)" X-Patchwork-Id: 11789043 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCC856CA for ; Mon, 21 Sep 2020 09:53:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 91A1C218AC for ; Mon, 21 Sep 2020 09:53:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="CuZ1dl1z" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 91A1C218AC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=/yYrNdFLn/e7eMKyLTwLBmMJzfciQMCngd/FL/mtU2I=; b=CuZ1dl1z8AriFXxXxRKkjzc0EJ zTqZX2uhbKYl1uE0YqlArFmonO26GAStATF9YOjTYzU0bTjVCul3VcUU8Dd01lCCPLH+XiDFvMXOb 3m3BiLwTL16GO3QjOgtQg+mYEmm9DsIhlhyIgO3Kqh/1XoPtDoVjEFQcCcwNxHSd26dt9HBmcWafg jY9CVqGxRRogfGQQcE6ow9Cdp2024p/wUwnepafcTNxARzNK+CWX8dwO8x8ewEG/eL/GWxURw1+Jn hsWEIQEPg9LcsVQ8LuK5Fg7LDZ23M+s2yx0Qu17ImGLTavBwQ5CQZ3CjowGPZAD73fkjTU4t0mQu0 mUuDduvQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKIUi-00032r-7T; Mon, 21 Sep 2020 09:52:24 +0000 Received: from szxga05-in.huawei.com ([45.249.212.191] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKIUe-0002y1-Al for linux-arm-kernel@lists.infradead.org; Mon, 21 Sep 2020 09:52:21 +0000 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id CDC19F919099F431C62D; Mon, 21 Sep 2020 17:52:01 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Mon, 21 Sep 2020 17:51:54 +0800 From: Qi Liu To: , , , Subject: [PATCH v2] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM Date: Mon, 21 Sep 2020 17:50:42 +0800 Message-ID: <1600681842-9105-1-git-send-email-liuqi115@huawei.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200921_055220_656971_A5D7571D X-CRM114-Status: GOOD ( 14.97 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [45.249.212.191 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [45.249.212.191 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The ETM device can't keep up with the core pipeline when cpu core is at full speed. This may cause overflow within core and its ETM. This is a common phenomenon on ETM devices. On HiSilicon Hip08 platform, a specific feature is added to set core pipeline. So commit rate can be reduced manually to avoid ETM overflow. Signed-off-by: Qi Liu --- Change since v1: - add CONFIG_ETM4X_IMPDEF_FEATURE and CONFIG_ETM4X_IMPDEF_HISILICON to keep specific feature off platforms which don't use it. drivers/hwtracing/coresight/Kconfig | 13 ++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 60 +++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) -- 2.8.1 diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 02dbb5c..362dadf 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -85,6 +85,19 @@ config CORESIGHT_SOURCE_ETM4X for instruction level tracing. Depending on the implemented version data tracing may also be available. +config ETM4X_IMPDEF_FEATURE + bool "Control overflow impdef support in CoreSight ETM 4.x driver " + depends on CORESIGHT_SOURCE_ETM4X + help + This control provides overflow impdef for CoreSight ETM 4.x driver + which can not reduce commit race automatically. + +config ETM4X_IMPDEF_HISILICON + bool "Control overflow impdef support in HiSilicon ETM 4.x driver " + depends on ETM4X_IMPDEF_FEATURE + help + This control provides overflow impdef for HiSilicon ETM 4.x driver. + config CORESIGHT_STM bool "CoreSight System Trace Macrocell driver" depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index f5ab13a..1a7a6c9 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -103,12 +103,71 @@ struct etm4_enable_arg { int rc; }; +#ifdef CONFIG_ETM4X_IMPDEF_FEATURE + +#ifdef CONFIG_ETM4X_IMPDEF_HISILICON + +#define HISI_HIP08_CORE_COMMIT_CLEAR 0x3000 +#define HISI_HIP08_CORE_COMMIT_SHIFT 12 +static void etm4_hisi_config_core_commit(int flag) +{ + u64 val; + + asm volatile("mrs %0,s3_1_c15_c2_5" : "=r"(val)); + val &= ~HISI_HIP08_CORE_COMMIT_CLEAR; + val |= flag << HISI_HIP08_CORE_COMMIT_SHIFT; + asm volatile("msr s3_1_c15_c2_5,%0" : : "r"(val)); +} +#else +static void etm4_hisi_config_core_commit(int flag) +{ +} +#endif /* CONFIG_ETM4X_IMPDEF_HISILICON */ + +static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) +{ + struct device *dev = drvdata->csdev->dev.parent; + struct amba_device *adev; + + adev = container_of(dev, struct amba_device, dev); + + /* + * If ETM device is HiSilicon ETM device, reduce the + * core-commit to avoid ETM overflow. + */ + etm4_hisi_config_core_commit(1); +} + +static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) +{ + struct device *dev = drvdata->csdev->dev.parent; + struct amba_device *adev; + + adev = container_of(dev, struct amba_device, dev); + + /* + * If ETM device is HiSilicon ETM device, resume the + * core-commit after ETM trace is complete. + */ + etm4_hisi_config_core_commit(0); +} +#else +static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) +{ +} + +static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) +{ +} +#endif/* CONFIG_ETM4X_IMPDEF_FEATURE */ + static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; struct etmv4_config *config = &drvdata->config; struct device *etm_dev = &drvdata->csdev->dev; + etm4_enable_arch_specific(drvdata); CS_UNLOCK(drvdata->base); etm4_os_unlock(drvdata); @@ -475,6 +534,7 @@ static void etm4_disable_hw(void *info) struct device *etm_dev = &drvdata->csdev->dev; int i; + etm4_disable_arch_specific(drvdata); CS_UNLOCK(drvdata->base); if (!drvdata->skip_power_up) {