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Thu, 8 Oct 2020 07:16:35 +0000 (GMT) From: Maninder Singh To: linux@armlinux.org.uk, ndesaulniers@google.com, caij2003@gmail.com, tglx@linutronix.de, bigeasy@linutronix.de, maz@kernel.org, valentin.schneider@arm.com, vincent.whitchurch@axis.com, nhuck@google.com, akpm@linux-foundation.org, 0x7f454c46@gmail.com, will@kernel.org Subject: [PATCH 2/3] arm: introduce IRQ stacks Date: Thu, 8 Oct 2020 12:45:32 +0530 Message-Id: <1602141333-17822-3-git-send-email-maninder1.s@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1602141333-17822-1-git-send-email-maninder1.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSf0xTVxjdfe+1fZRU31oSLwVZ7MYCJisYNN4wU0fitpeRZWzGP3TRWuWl JULBPn6HCBumm52zwAojXWmJVjcZIi0o0FomxQ1QV1dJIFUwzCERyKRQCWOAzvZB9t853znn O19uLomLHTwpmaMtZHRaVa6MLySu9ycnvZPgOaVMfXFBjmoanhLI72aQ5WorHzX463B02doD kPOvER4adln4yFvvAajfpidQj2WIh4I1LzHU0b9AoA5nPY68Q00AddmWcXTv+ifo9Niu916n W62tgB4e8eP0aFsW3WMeF9DNziLa2XKGTz/z+QT0YOMKQXfYK+lznS2ADjkTsqIPCfdkM7k5 xYwuRXFUqPF0dQsKBpNKXb1GQRVYizeAKBJSO6HlOzfPAISkmHID2Gj/EufIAoChpyY87BJT IQC/dkdvJLpCVYCbuwB0tGVzgUUAgz1TEYFPyWGL6wYRFmIoEwatiz9GCE6dB9DiN0Zcklcu i9UgCGOCSoR/9C1EsIj6ELpHG3lcXQIM+M68OoMkoygars0nh/dA6gYJl/v+5XOefXDt5iOC wxI4M9Ap4LAUThv1Ai5QDeBC7xXAEROAF/3z6w174Wx1FRZuwKlkeNWVwo23wvrbbVgY49Qm +O3KJMbNRbDbuoET4elA+/qaOBian18/gobnayzrr/oDgBOuYV4NSDD/X9EMQAuIZQrYPDXD 7ipI0zIlclaVxxZp1fLj+XlOEPlV2zO7weOJoNwLMBJ4ASRxWYxInVmhFIuyVWXljC5fqSvK ZVgviCMJ2RaR7J+7R8SUWlXInGCYAka3oWJklLQKG7ifLtz0gUkxdu+O5LX91z6akdaa399s fKYvU2TFja7GeT4fYd8eadp2aUaQ+Vt5TL5tqilWVFdmXHG8wauNest+NjX2z4rE2Vu3HeMl jgO9SiOxI6jYvBofKG19UDq3zy5tt+pW2YxjJz9+0nBhbaz8YMwW2/jf08uBSfLSL7WK37ee PLukf/lZHfwp/eHcFxMH5dScxn9nUD/15OflSW8wPcn8LjI0ZyivlBbm7M5pX+xLGzZYnzcq H3auTp9LPXYEVo+9KHGErL5PNZYBjR97M1sdf6ty91IKUTwr8Xzz1R6fNnqItn1/eKlY8ZhO M9+0V0oOB37da9q/7ZqiwpghI1iNasd2XMeq/gPOHennxAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRmVeSWpSXmKPExsWy7bCSnO61PXXxBnP/mltMmPaCxeLi7lSL OevXsFlMuziJ2WLlvJ2MFpseX2O1uLxrDpvFoal7GS0Oz29jsdg55ySrxYcJ/5ksNh/+xGKx edNUZotDJ+cyWmyf/5PZ4vw2f4uWO6YOgh5r5q1h9Lh87SKzx/V1AR47Z91l91iwqdRj06pO No93586xe5yY8ZvFY/OSeo++LasYPT5vkgvgjuKySUnNySxLLdK3S+DK2Lt9B3vBCY2KXfv6 2RsY/8p0MXJySAiYSGz/3MDYxcjFISSwg1Fiz47NrBAJaYmf/96zQNjCEiv/PWeHKPrMKHHr 7U92kASbgJ7Eql17WEASIgJLmCSOXprMCuIwCyxjlGj/uxZslDBQ1Zx5XWAdLAKqEhcOfgKz eQXcJXZfnwG1Tk7i5rlO5i5GDg5OAQ+Jvx81QcJCQCUTu+6yTmDkW8DIsIpRMrWgODc9t9iw wCgvtVyvODG3uDQvXS85P3cTIzgatLR2MO5Z9UHvECMTB+MhRgkOZiUR3nTvmngh3pTEyqrU ovz4otKc1OJDjNIcLErivF9nLYwTEkhPLEnNTk0tSC2CyTJxcEo1MJ1T+Fh58a54TMa/6sX/ uKRX/d4R5VKZt1H44x9NDVXfTI5QH6G3j1YJ/LZZcTTx7ck/K4yfLBOqkVJZEGNg5nd18hKL l2vMpY4uuP/lQtgJrZnBSQtf88/tP7j18CojQZlzrxJ+TMk4u84oqi/f2u2QkbeYg8qKX9ZT 05+/XKSgfC9TRVRUczOXZrbBzqWXfXOyvufGHOF8wPGWbe7r/GzPXUpWLSVT0260fdi8yv3l pO1Be7m2r2m1/v3NsvDL8yzFzyK9R4LSZs16LCqf/EvhP0teXkHi64U+l5Itr3N9s0s7tofV 5ZT65y3bXi0qPFHfwP/uy+5W/Q1z0ne1pE7f/KdZxeXhNMVGrgthSWeUWIozEg21mIuKEwHn VyUa9QIAAA== X-CMS-MailID: 20201008071639epcas5p465f13d992a25936ba63436baf1fb6f83 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20201008071639epcas5p465f13d992a25936ba63436baf1fb6f83 References: <1602141333-17822-1-git-send-email-maninder1.s@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201008_031756_209570_EE0A5FED X-CRM114-Status: GOOD ( 20.33 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [203.254.224.33 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [203.254.224.33 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders -0.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: v.narang@samsung.com, Maninder Singh , a.sahrawat@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds code for switching to IRQ stack. IRQ stack and Kernel SVC stack have below design. IRQ STACK:- ------------ IRQ stack top | | ------------ . . . . . . ------------ | sp | <- irq_stack_base + 0x8 ------------ | fp | <- irq_stack_base + 0x4 ------------ |tinfo_ptr | /* pointer to thread info */ irq_stack_ptr --> ------------ IRQ stack base Kernel SVC stack:- ------------ Kernel stack top | | ------------ . . . . . . ------------ | | | | ------------ |tinfo_ptr | /* pointer to thread info */ ------------ Kernel stack base Co-developed-by: Vaneet Narang Signed-off-by: Vaneet Narang Signed-off-by: Maninder Singh --- arch/arm/include/asm/assembler.h | 8 ++++++++ arch/arm/include/asm/irq.h | 6 ++++++ arch/arm/kernel/entry-armv.S | 41 +++++++++++++++++++++++++++++++++++++++- arch/arm/kernel/irq.c | 24 +++++++++++++++++++++++ 4 files changed, 78 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 8512bdc..82ee6ee 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -212,6 +212,14 @@ #endif .endm + .macro this_cpu_ptr, sym, reg, tmp + ldr \reg, =\sym +#if defined(CONFIG_SMP) && !defined(CONFIG_CPU_V6) + mrc p15, 0, \tmp, cr13, c0, 4 + add \reg, \reg, \tmp +#endif + .endm + /* * Increment/decrement the preempt count. */ diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index 46d4114..f3299ab 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -22,10 +22,16 @@ #define NO_IRQ ((unsigned int)(-1)) #endif +#define IRQ_STACK_SIZE THREAD_SIZE + #ifndef __ASSEMBLY__ struct irqaction; struct pt_regs; +#ifdef CONFIG_IRQ_STACK +DECLARE_PER_CPU(unsigned long *, irq_stack_ptr); +#endif + extern void asm_do_IRQ(unsigned int, struct pt_regs *); void handle_IRQ(unsigned int, struct pt_regs *); void init_IRQ(void); diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 55a47df..13a5889 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -32,6 +32,43 @@ #include "entry-header.S" #include #include +#ifdef CONFIG_IRQ_STACK +#include +#endif + + .macro irq_stack_entry +#ifdef CONFIG_IRQ_STACK + mov r6, sp /* preserve sp */ + + this_cpu_ptr irq_stack_ptr, r7, r8 + ldr r7, [r7] + mov r8, r7 + + /* + * Compare sp with base of IRQ stack. + * if the top ~(#THREAD_SIZE_ORDER + PAGE_SHIFT) bits match, + * we are on a irq stack. + */ + eor r8, r8, sp + lsrs r8, #THREAD_SIZE_ORDER + PAGE_SHIFT + beq 9998f + + /* + * store thread info pointer on IRQ stack and + * switch to the irq stack. + */ + get_thread_info r8 + stm r7, {r8, fp, sp} + add sp, r7, #IRQ_STACK_SIZE +9998: +#endif + .endm + + .macro irq_stack_exit +#ifdef CONFIG_IRQ_STACK + mov sp, r6 /* restore sp */ +#endif + .endm /* * Interrupt handling. @@ -41,11 +78,13 @@ ldr r1, =handle_arch_irq mov r0, sp badr lr, 9997f + irq_stack_entry ldr pc, [r1] +9997: + irq_stack_exit #else arch_irq_handler_default #endif -9997: .endm .macro pabt_helper diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 698b6f6..79872e5 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -43,6 +43,15 @@ unsigned long irq_err_count; +#ifdef CONFIG_IRQ_STACK +DEFINE_PER_CPU(unsigned long *, irq_stack_ptr); + +/* + * irq_stack must be IRQ_STACK_SIZE(THREAD_SIZE) aligned, + */ +DEFINE_PER_CPU(unsigned long [IRQ_STACK_SIZE/sizeof(long)], irq_stack) __aligned(IRQ_STACK_SIZE); +#endif + int arch_show_interrupts(struct seq_file *p, int prec) { #ifdef CONFIG_FIQ @@ -55,6 +64,20 @@ int arch_show_interrupts(struct seq_file *p, int prec) return 0; } +#ifdef CONFIG_IRQ_STACK +static void init_irq_stacks(void) +{ + int cpu; + + for_each_possible_cpu(cpu) + per_cpu(irq_stack_ptr, cpu) = per_cpu(irq_stack, cpu); +} +#else +static inline void init_irq_stacks(void) +{ +} +#endif + /* * handle_IRQ handles all hardware IRQ's. Decoded IRQs should * not come via this function. Instead, they should provide their @@ -79,6 +102,7 @@ void __init init_IRQ(void) { int ret; + init_irq_stacks(); if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq) irqchip_init(); else