| Message ID | 1602766748-25490-2-git-send-email-hsin-hsiung.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add SPMI support for Mediatek MT6873/8192 SoC IC | expand |
Quoting Hsin-Hsiung Wang (2020-10-15 05:59:07) > This adds documentation for the SPMI controller found on Mediatek SoCs. > > Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> I don't know what's going on but my MUA sees a bunch of CRLF line endings in these patches. > diff --git a/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.yaml > new file mode 100644 > index 000000000000..39459ca2e0da > --- /dev/null > +++ b/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/spmi/spmi-mtk-pmif.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek SPMI Controller Device Tree Bindings > + > +maintainers: > + - Stephen Boyd <sboyd@kernel.org> > + - Matthias Brugger <matthias.bgg@gmail.com> Is there someone at mediatek who can be the maintainer of this binding? > + > +description: |+ What's up with the plus? > + On MediaTek SoCs the PMIC is connected via SPMI and the controller allows > + for multiple SoCs to control a single SPMI master. > + > +properties: > + compatible: > + const: mediatek,mt6873-spmi > + > + reg: > + minItems: 2 > + maxItems: 2 > + > + reg-names: > + items: > + - const: "pmif" > + - const: "spmimst" > + > + clocks: > + minItems: 3 > + maxItems: 3 > + > + clock-names: > + items: > + - const: "pmif_sys_ck" > + - const: "pmif_tmr_ck" > + - const: "spmimst_clk_mux" > + > + assigned-clocks: > + maxItems: 1 > + > + assigned-clock-parents: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - reg-names Is reg-names really required? > + - clocks > + - clock-names I think we need additionalProperties: False here > + > +examples: > + - | > + #include <dt-bindings/clock/mt8192-clk.h> > + > + spmi: spmi@10027000 { > + compatible = "mediatek,mt6873-spmi"; > + reg = <0 0x10027000 0 0x000e00>, > + <0 0x10029000 0 0x000100>; I think we can drop the two cells and just have one cell binding here? > + reg-names = "pmif", "spmimst"; > + clocks = <&infracfg CLK_INFRA_PMIC_AP>, > + <&infracfg CLK_INFRA_PMIC_TMR>, > + <&topckgen CLK_TOP_SPMI_MST_SEL>; > + clock-names = "pmif_sys_ck", > + "pmif_tmr_ck", > + "spmimst_clk_mux"; > + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; > + }; > +...
diff --git a/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.yaml new file mode 100644 index 000000000000..39459ca2e0da --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/spmi-mtk-pmif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek SPMI Controller Device Tree Bindings + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Matthias Brugger <matthias.bgg@gmail.com> + +description: |+ + On MediaTek SoCs the PMIC is connected via SPMI and the controller allows + for multiple SoCs to control a single SPMI master. + +properties: + compatible: + const: mediatek,mt6873-spmi + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: "pmif" + - const: "spmimst" + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: "pmif_sys_ck" + - const: "pmif_tmr_ck" + - const: "spmimst_clk_mux" + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/mt8192-clk.h> + + spmi: spmi@10027000 { + compatible = "mediatek,mt6873-spmi"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; +...
This adds documentation for the SPMI controller found on Mediatek SoCs. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> --- .../bindings/spmi/spmi-mtk-pmif.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/spmi/spmi-mtk-pmif.yaml