From patchwork Wed Oct 21 12:40:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11849011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 711F2C388F9 for ; Wed, 21 Oct 2020 12:42:25 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 07DC32177B for ; Wed, 21 Oct 2020 12:42:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="z0UMykO8" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 07DC32177B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=KBdh7hyfvQl7+BUfAO6C/xc+DkdwlwPWQswUKe673rg=; b=z0UMykO8y3IqndEpkudkSc+znt sKG5DHJZtMSRn9lBwsYyYsl6F0+R7liTbWouTjF6Yk2cGWg0zrETSlUR1GQ7YZXZ/Mgan8OCfjqLx wOSfRyzV5LLHQzlcvf/qrw3+VQoLF4B7bu1/k++zwfbJfiVjHtDlnTh+KKaRsDKv/58efBkHVH7SJ 2YuIPetWSXYBghTzZL9/RxPIbwAhVKXGQxGw1Mn2QCU/nIIbirtgcgnYwOeymMuEGZnic+zF6xSrQ kUC2QZ4yyGLy8gcoHARRwhwP2QjZXpZq87GhlJCv8n3jTbQn0rla8u9H0VRBj+GP3eMPP5bOyP6ku g6I2O21A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVDQJ-0006aV-6x; Wed, 21 Oct 2020 12:40:59 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVDQG-0006YX-5Y for linux-arm-kernel@lists.infradead.org; Wed, 21 Oct 2020 12:40:56 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 77F491A0C22; Wed, 21 Oct 2020 14:40:54 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6AF851A0C2B; Wed, 21 Oct 2020 14:40:54 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 9B9A2203A1; Wed, 21 Oct 2020 14:40:53 +0200 (CEST) From: Abel Vesa To: Shawn Guo , Stephen Boyd , Peng Fan , Dong Aisheng , Anson Huang Subject: [PATCH 1/2] clk: imx: composite-8m: Add DRAM clock registration variant Date: Wed, 21 Oct 2020 15:40:42 +0300 Message-Id: <1603284043-27059-2-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1603284043-27059-1-git-send-email-abel.vesa@nxp.com> References: <1603284043-27059-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201021_084056_311448_614DE5C8 X-CRM114-Status: GOOD ( 11.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linux Kernel Mailing List , Abel Vesa , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The switch between parents for dram_apb and dram_alt is done in EL3, so lets mark the mux and divider as read only with the CLK_DIVIDER_READ_ONLY and CLK_MUX_READ_ONLY flags. Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-composite-8m.c | 7 +++++++ drivers/clk/imx/clk.h | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 2c309e3..c3231eb 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -211,6 +211,13 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, div->width = PCG_PREDIV_WIDTH; divider_ops = &imx8m_clk_composite_divider_ops; mux_ops = &imx8m_clk_composite_mux_ops; + } else if (composite_flags & IMX_COMPOSITE_DRAM) { + div->shift = PCG_PREDIV_SHIFT; + div->width = PCG_PREDIV_WIDTH; + div->flags = CLK_DIVIDER_READ_ONLY; + mux->flags = CLK_MUX_READ_ONLY; + divider_ops = &clk_divider_ops; + mux_ops = &clk_mux_ops; } else { div->shift = PCG_PREDIV_SHIFT; div->width = PCG_PREDIV_WIDTH; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 3b796b3..70c57d2 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -535,6 +535,7 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, #define IMX_COMPOSITE_CORE BIT(0) #define IMX_COMPOSITE_BUS BIT(1) +#define IMX_COMPOSITE_DRAM BIT(2) struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, const char * const *parent_names, @@ -565,6 +566,11 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, ARRAY_SIZE(parent_names), reg, 0, \ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) +#define __imx8m_clk_hw_composite_dram(name, parent_names, reg, flags) \ + imx8m_clk_hw_composite_flags(name, parent_names, \ + ARRAY_SIZE(parent_names), reg, IMX_COMPOSITE_DRAM, \ + flags | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE) + #define __imx8m_clk_composite(name, parent_names, reg, flags) \ to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))