From patchwork Sun Jan 24 15:09:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 12042443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 879E7C433E0 for ; Sun, 24 Jan 2021 15:11:18 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 48BC522B2C for ; Sun, 24 Jan 2021 15:11:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 48BC522B2C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BLoKkZeus/6TzAE9XM8FPtEI6L8BH9yPDk4zEdRmUp4=; b=HI/NRHNgNJesP2VYPSlt3yG04J Jk+B/jP1Ug9aZpHQPFMGFCpFSn+InFg4NEWx0IMORYQnHyLNUtcxIgbVQC8VCxuJS7Mg1iY30IYw9 1/Fjo4RoHcdWAl90B5BOdIh3Mj0rl1/Soga4J8QV0DJWA7zSEGKe362oyZkD07HgJfnn3l7Chi1HM yKVOV6ktuJCl90YSQWPVLMu/A6IrM3911zyBFw+uvZiwLSUfzQB0gfyg5cRDqenMl1n0Qjml36bDW n6BzEq8Rp4LVVyhm7661R8lwb+Ybe/vLVX1iV5Y5MR7rPIOAQ1ZorcOuKliHQuXyvetN36Ve2RuoV +xiZcn1w==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l3h1b-0003lg-Rf; Sun, 24 Jan 2021 15:09:59 +0000 Received: from mx.socionext.com ([202.248.49.38]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l3h1O-0003j9-Vx for linux-arm-kernel@lists.infradead.org; Sun, 24 Jan 2021 15:09:48 +0000 Received: from unknown (HELO kinkan2-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 25 Jan 2021 00:09:46 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan2-ex.css.socionext.com (Postfix) with ESMTP id 1EB7A2059027; Mon, 25 Jan 2021 00:09:46 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 25 Jan 2021 00:09:46 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan2.css.socionext.com (Postfix) with ESMTP id D3FE2B1D40; Mon, 25 Jan 2021 00:09:45 +0900 (JST) From: Kunihiko Hayashi To: Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I Subject: [PATCH v2 3/3] PCI: uniphier-ep: Add EPC restart management support Date: Mon, 25 Jan 2021 00:09:37 +0900 Message-Id: <1611500977-24816-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611500977-24816-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1611500977-24816-1-git-send-email-hayashi.kunihiko@socionext.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210124_100947_411069_3C1324C0 X-CRM114-Status: GOOD ( 22.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kunihiko Hayashi , Masami Hiramatsu , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Set the polling function and call the init function to enable EPC restart management. The polling function detects that the bus-reset signal is a rising edge. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-uniphier-ep.c | 44 ++++++++++++++++++++++++++- 2 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 22c5529..90d400a 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -302,6 +302,7 @@ config PCIE_UNIPHIER_EP depends on OF && HAS_IOMEM depends on PCI_ENDPOINT select PCIE_DW_EP + select PCI_ENDPOINT_RESTART help Say Y here if you want PCIe endpoint controller support on UniPhier SoCs. This driver supports Pro5 SoC. diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c index 69810c6..9d83850 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c @@ -26,6 +26,7 @@ #define PCL_RSTCTRL_PIPE3 BIT(0) #define PCL_RSTCTRL1 0x0020 +#define PCL_RSTCTRL_PERST_MON BIT(16) #define PCL_RSTCTRL_PERST BIT(0) #define PCL_RSTCTRL2 0x0024 @@ -60,6 +61,7 @@ struct uniphier_pcie_ep_priv { struct clk *clk, *clk_gio; struct reset_control *rst, *rst_gio; struct phy *phy; + bool bus_reset_status; const struct pci_epc_features *features; }; @@ -212,6 +214,41 @@ uniphier_pcie_get_features(struct dw_pcie_ep *ep) return priv->features; } +static bool uniphier_pcie_ep_poll_reset(void *data) +{ + struct uniphier_pcie_ep_priv *priv = data; + bool ret, status; + + if (!priv) + return false; + + status = !(readl(priv->base + PCL_RSTCTRL1) & PCL_RSTCTRL_PERST_MON); + + /* return true if the rising edge of bus reset is detected */ + ret = !!(status == false && priv->bus_reset_status == true); + priv->bus_reset_status = status; + + return ret; +} + +static int uniphier_pcie_ep_init_complete(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci); + int ret; + + /* Set up epc-restart thread */ + pci_epc_restart_register_poll_func(ep->epc, + uniphier_pcie_ep_poll_reset, priv); + /* With call of poll_reset() directly, initialize internal state */ + uniphier_pcie_ep_poll_reset(priv); + ret = pci_epc_restart_init(ep->epc); + if (ret) + dev_err(pci->dev, "Failed to initialize epc-restart (%d)\n", ret); + + return ret; +} + static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = { .ep_init = uniphier_pcie_ep_init, .raise_irq = uniphier_pcie_ep_raise_irq, @@ -318,7 +355,12 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev) return ret; priv->pci.ep.ops = &uniphier_pcie_ep_ops; - return dw_pcie_ep_init(&priv->pci.ep); + + ret = dw_pcie_ep_init(&priv->pci.ep); + if (ret) + return ret; + + return uniphier_pcie_ep_init_complete(&priv->pci.ep); } static const struct pci_epc_features uniphier_pro5_data = {