diff mbox series

[V3,10/14] arm64: nvhe: Allow TRBE access at EL1

Message ID 1611737738-1493-11-git-send-email-anshuman.khandual@arm.com (mailing list archive)
State New
Headers show
Series arm64: coresight: Enable ETE and TRBE | expand

Commit Message

Anshuman Khandual Jan. 27, 2021, 8:55 a.m. UTC
From: Suzuki K Poulose <suzuki.poulose@arm.com>

When the kernel is booted at EL2 in a nvhe configuration,
enable the TRBE access to the EL1. The EL1 still can't trace
EL2, unless EL2 permits explicitly via TRFCR_EL2.E2TRE.

Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
cc: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/include/asm/el2_setup.h | 19 +++++++++++++++++++
 arch/arm64/include/asm/kvm_arm.h   |  2 ++
 2 files changed, 21 insertions(+)

Comments

Marc Zyngier Jan. 27, 2021, 9:58 a.m. UTC | #1
On 2021-01-27 08:55, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> When the kernel is booted at EL2 in a nvhe configuration,
> enable the TRBE access to the EL1. The EL1 still can't trace
> EL2, unless EL2 permits explicitly via TRFCR_EL2.E2TRE.
> 
> Cc: Will Deacon <will@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>

Acked-by: Marc Zyngier <maz@kernel.org>

One comment below, though:

> ---
>  arch/arm64/include/asm/el2_setup.h | 19 +++++++++++++++++++
>  arch/arm64/include/asm/kvm_arm.h   |  2 ++
>  2 files changed, 21 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/el2_setup.h
> b/arch/arm64/include/asm/el2_setup.h
> index a7f5a1b..05ecce9 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -72,6 +72,25 @@
>  .endif
> 
>  3:
> +
> +.ifeqs	"\mode", "nvhe"
> +	/*
> +	 * If the Trace Buffer is available, allow
> +	 * the EL1 to own it. Note that EL1 cannot
> +	 * trace the EL2, as it is prevented by
> +	 * TRFCR_EL2.E2TRE == 0.
> +	 */
> +	ubfx	x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
> +	cbz	x0, 1f
> +
> +	mrs_s	x0, SYS_TRBIDR_EL1
> +	and	x0, x0, TRBIDR_PROG
> +	cbnz	x0, 1f
> +	mov	x0, #(MDCR_EL2_E2TB_EL1_OWN << MDCR_EL2_E2TB_SHIFT)
> +	orr	x2, x2, x0
> +.endif
> +
> +1:

Note that this will (badly) conflict with the late-VHE patches[1],
where this code path has been reworked.

Thanks,

         M.

[1] https://lore.kernel.org/r/20210125105019.2946057-1-maz@kernel.org
Suzuki K Poulose Jan. 28, 2021, 9:34 a.m. UTC | #2
On 1/27/21 9:58 AM, Marc Zyngier wrote:
> On 2021-01-27 08:55, Anshuman Khandual wrote:
>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> When the kernel is booted at EL2 in a nvhe configuration,
>> enable the TRBE access to the EL1. The EL1 still can't trace
>> EL2, unless EL2 permits explicitly via TRFCR_EL2.E2TRE.
>>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> cc: Anshuman Khandual <anshuman.khandual@arm.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> 
> Acked-by: Marc Zyngier <maz@kernel.org>
> 
> One comment below, though:
> 
>> ---
>>  arch/arm64/include/asm/el2_setup.h | 19 +++++++++++++++++++
>>  arch/arm64/include/asm/kvm_arm.h   |  2 ++
>>  2 files changed, 21 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/el2_setup.h
>> b/arch/arm64/include/asm/el2_setup.h
>> index a7f5a1b..05ecce9 100644
>> --- a/arch/arm64/include/asm/el2_setup.h
>> +++ b/arch/arm64/include/asm/el2_setup.h
>> @@ -72,6 +72,25 @@
>>  .endif
>>
>>  3:
>> +
>> +.ifeqs    "\mode", "nvhe"
>> +    /*
>> +     * If the Trace Buffer is available, allow
>> +     * the EL1 to own it. Note that EL1 cannot
>> +     * trace the EL2, as it is prevented by
>> +     * TRFCR_EL2.E2TRE == 0.
>> +     */
>> +    ubfx    x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
>> +    cbz    x0, 1f
>> +
>> +    mrs_s    x0, SYS_TRBIDR_EL1
>> +    and    x0, x0, TRBIDR_PROG
>> +    cbnz    x0, 1f
>> +    mov    x0, #(MDCR_EL2_E2TB_EL1_OWN << MDCR_EL2_E2TB_SHIFT)
>> +    orr    x2, x2, x0
>> +.endif
>> +
>> +1:
> 
> Note that this will (badly) conflict with the late-VHE patches[1],
> where this code path has been reworked.

Thanks for the heads up. We will need to see how things get merged.
Ideally this patch and the previous one (TRBE definitions could go
via the arm64 tree / kvm tree), in which case we could rebase these
two patches on the respective tree.

Cheers
Suzuki
Marc Zyngier Jan. 28, 2021, 9:46 a.m. UTC | #3
On 2021-01-28 09:34, Suzuki K Poulose wrote:
> On 1/27/21 9:58 AM, Marc Zyngier wrote:
>> On 2021-01-27 08:55, Anshuman Khandual wrote:
>>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> 
>>> When the kernel is booted at EL2 in a nvhe configuration,
>>> enable the TRBE access to the EL1. The EL1 still can't trace
>>> EL2, unless EL2 permits explicitly via TRFCR_EL2.E2TRE.
>>> 
>>> Cc: Will Deacon <will@kernel.org>
>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>> Cc: Marc Zyngier <maz@kernel.org>
>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>> cc: Anshuman Khandual <anshuman.khandual@arm.com>
>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> 
>> Acked-by: Marc Zyngier <maz@kernel.org>
>> 
>> One comment below, though:
>> 
>>> ---
>>>  arch/arm64/include/asm/el2_setup.h | 19 +++++++++++++++++++
>>>  arch/arm64/include/asm/kvm_arm.h   |  2 ++
>>>  2 files changed, 21 insertions(+)
>>> 
>>> diff --git a/arch/arm64/include/asm/el2_setup.h
>>> b/arch/arm64/include/asm/el2_setup.h
>>> index a7f5a1b..05ecce9 100644
>>> --- a/arch/arm64/include/asm/el2_setup.h
>>> +++ b/arch/arm64/include/asm/el2_setup.h
>>> @@ -72,6 +72,25 @@
>>>  .endif
>>> 
>>>  3:
>>> +
>>> +.ifeqs    "\mode", "nvhe"
>>> +    /*
>>> +     * If the Trace Buffer is available, allow
>>> +     * the EL1 to own it. Note that EL1 cannot
>>> +     * trace the EL2, as it is prevented by
>>> +     * TRFCR_EL2.E2TRE == 0.
>>> +     */
>>> +    ubfx    x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
>>> +    cbz    x0, 1f
>>> +
>>> +    mrs_s    x0, SYS_TRBIDR_EL1
>>> +    and    x0, x0, TRBIDR_PROG
>>> +    cbnz    x0, 1f
>>> +    mov    x0, #(MDCR_EL2_E2TB_EL1_OWN << MDCR_EL2_E2TB_SHIFT)
>>> +    orr    x2, x2, x0
>>> +.endif
>>> +
>>> +1:
>> 
>> Note that this will (badly) conflict with the late-VHE patches[1],
>> where this code path has been reworked.
> 
> Thanks for the heads up. We will need to see how things get merged.
> Ideally this patch and the previous one (TRBE definitions could go
> via the arm64 tree / kvm tree), in which case we could rebase these
> two patches on the respective tree.

I think the current plan of action is to go via the arm64 tree,
given that there is nothing really KVM specific there. I'll respin
the series one last (hopefully!) time on Monday. Let me know if
you need a hand with the rebasing.

Thanks,

         M.
Suzuki K Poulose Jan. 28, 2021, 9:48 a.m. UTC | #4
On 1/28/21 9:46 AM, Marc Zyngier wrote:
> On 2021-01-28 09:34, Suzuki K Poulose wrote:
>> On 1/27/21 9:58 AM, Marc Zyngier wrote:
>>> On 2021-01-27 08:55, Anshuman Khandual wrote:
>>>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>>>
>>>> When the kernel is booted at EL2 in a nvhe configuration,
>>>> enable the TRBE access to the EL1. The EL1 still can't trace
>>>> EL2, unless EL2 permits explicitly via TRFCR_EL2.E2TRE.
>>>>
>>>> Cc: Will Deacon <will@kernel.org>
>>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>>> Cc: Marc Zyngier <maz@kernel.org>
>>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>>> cc: Anshuman Khandual <anshuman.khandual@arm.com>
>>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>>>
>>> Acked-by: Marc Zyngier <maz@kernel.org>
>>>
>>> One comment below, though:
>>>
>>>> ---
>>>>  arch/arm64/include/asm/el2_setup.h | 19 +++++++++++++++++++
>>>>  arch/arm64/include/asm/kvm_arm.h   |  2 ++
>>>>  2 files changed, 21 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/include/asm/el2_setup.h
>>>> b/arch/arm64/include/asm/el2_setup.h
>>>> index a7f5a1b..05ecce9 100644
>>>> --- a/arch/arm64/include/asm/el2_setup.h
>>>> +++ b/arch/arm64/include/asm/el2_setup.h
>>>> @@ -72,6 +72,25 @@
>>>>  .endif
>>>>
>>>>  3:
>>>> +
>>>> +.ifeqs    "\mode", "nvhe"
>>>> +    /*
>>>> +     * If the Trace Buffer is available, allow
>>>> +     * the EL1 to own it. Note that EL1 cannot
>>>> +     * trace the EL2, as it is prevented by
>>>> +     * TRFCR_EL2.E2TRE == 0.
>>>> +     */
>>>> +    ubfx    x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
>>>> +    cbz    x0, 1f
>>>> +
>>>> +    mrs_s    x0, SYS_TRBIDR_EL1
>>>> +    and    x0, x0, TRBIDR_PROG
>>>> +    cbnz    x0, 1f
>>>> +    mov    x0, #(MDCR_EL2_E2TB_EL1_OWN << MDCR_EL2_E2TB_SHIFT)
>>>> +    orr    x2, x2, x0
>>>> +.endif
>>>> +
>>>> +1:
>>>
>>> Note that this will (badly) conflict with the late-VHE patches[1],
>>> where this code path has been reworked.
>>
>> Thanks for the heads up. We will need to see how things get merged.
>> Ideally this patch and the previous one (TRBE definitions could go
>> via the arm64 tree / kvm tree), in which case we could rebase these
>> two patches on the respective tree.
> 
> I think the current plan of action is to go via the arm64 tree,
> given that there is nothing really KVM specific there. I'll respin
> the series one last (hopefully!) time on Monday. Let me know if
> you need a hand with the rebasing.

Sounds good, will rebase it on top of that then.

Cheers
Suzuki
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index a7f5a1b..05ecce9 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -72,6 +72,25 @@ 
 .endif
 
 3:
+
+.ifeqs	"\mode", "nvhe"
+	/*
+	 * If the Trace Buffer is available, allow
+	 * the EL1 to own it. Note that EL1 cannot
+	 * trace the EL2, as it is prevented by
+	 * TRFCR_EL2.E2TRE == 0.
+	 */
+	ubfx	x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
+	cbz	x0, 1f
+
+	mrs_s	x0, SYS_TRBIDR_EL1
+	and	x0, x0, TRBIDR_PROG
+	cbnz	x0, 1f
+	mov	x0, #(MDCR_EL2_E2TB_EL1_OWN << MDCR_EL2_E2TB_SHIFT)
+	orr	x2, x2, x0
+.endif
+
+1:
 	msr	mdcr_el2, x2			// Configure debug traps
 .endm
 
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 4e90c2d..ed8b789 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -281,6 +281,8 @@ 
 #define MDCR_EL2_TPMS		(1 << 14)
 #define MDCR_EL2_E2PB_MASK	(UL(0x3))
 #define MDCR_EL2_E2PB_SHIFT	(UL(12))
+#define MDCR_EL2_E2TB_EL1_OWN	(UL(0x3))
+#define MDCR_EL2_E2TB_SHIFT	(UL(24))
 #define MDCR_EL2_TDRA		(1 << 11)
 #define MDCR_EL2_TDOSA		(1 << 10)
 #define MDCR_EL2_TDA		(1 << 9)