From patchwork Tue Feb 9 09:42:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "liuqi (BA)" X-Patchwork-Id: 12077591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E6C0C433E0 for ; Tue, 9 Feb 2021 09:46:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 440CD64E8A for ; Tue, 9 Feb 2021 09:46:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 440CD64E8A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=o8+6mMlgD7QWqCSaRFh9Ei56QzynnWCKS5InqNB28VM=; b=qnCS28rqINEMZvxy3uMJNGgoKY sTZnyr80lzWOUg/eW4z/+VqMywp5WvDIflWCMJjebvGWTCIRMTBNYtwY9D5LlVwNG53IaVdk6SKWl FrRUWtK7giLfg5Jo7e+XrzuVaIaBuU2dJVooQDD0DTSPHzx7Sukek5vBH67xXFDvOAiGJ5avvgRyF 0OGKvw1EdkSiXE2l7kb8vXGacAcRnKjaPLdoAEIREPW4D3DumjdAFbaqU0XeZT1T3CPotE570jqYa jhw5gfEDEuiuLGJ96B+iQOArtS24QNyXN9fiLvO726EpHSq9Bo5k/aQw2dGyjJrU/gkxzEwnfG3dR iX/RU2Og==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9PZp-0006ui-66; Tue, 09 Feb 2021 09:44:57 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l9PZm-0006tT-24 for linux-arm-kernel@lists.infradead.org; Tue, 09 Feb 2021 09:44:55 +0000 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DZdHD2X25zlHYF; Tue, 9 Feb 2021 17:43:04 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.498.0; Tue, 9 Feb 2021 17:44:39 +0800 From: Qi Liu To: , Subject: [PATCH] drivers/perf: Replace spin_lock_irqsave to spin_lock Date: Tue, 9 Feb 2021 17:42:22 +0800 Message-ID: <1612863742-1551-1-git-send-email-liuqi115@huawei.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210209_044454_354657_15CB93FA X-CRM114-Status: UNSURE ( 9.91 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There is no need to do spin_lock_irqsave in context of hard IRQ, so replace them with spin_lock. Signed-off-by: Qi Liu --- drivers/perf/arm-cci.c | 5 ++--- drivers/perf/xgene_pmu.c | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) -- 2.8.1 diff --git a/drivers/perf/arm-cci.c b/drivers/perf/arm-cci.c index a75cf77..f81e2ec 100644 --- a/drivers/perf/arm-cci.c +++ b/drivers/perf/arm-cci.c @@ -1026,12 +1026,11 @@ static void pmu_event_set_period(struct perf_event *event) static irqreturn_t pmu_handle_irq(int irq_num, void *dev) { - unsigned long flags; struct cci_pmu *cci_pmu = dev; struct cci_pmu_hw_events *events = &cci_pmu->hw_events; int idx, handled = IRQ_NONE; - raw_spin_lock_irqsave(&events->pmu_lock, flags); + raw_spin_lock(&events->pmu_lock); /* Disable the PMU while we walk through the counters */ __cci_pmu_disable(cci_pmu); @@ -1061,7 +1060,7 @@ static irqreturn_t pmu_handle_irq(int irq_num, void *dev) /* Enable the PMU and sync possibly overflowed counters */ __cci_pmu_enable_sync(cci_pmu); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); + raw_spin_unlock(&events->pmu_lock); return IRQ_RETVAL(handled); } diff --git a/drivers/perf/xgene_pmu.c b/drivers/perf/xgene_pmu.c index 633cf07..44faa51 100644 --- a/drivers/perf/xgene_pmu.c +++ b/drivers/perf/xgene_pmu.c @@ -1234,10 +1234,9 @@ static irqreturn_t xgene_pmu_isr(int irq, void *dev_id) u32 intr_mcu, intr_mcb, intr_l3c, intr_iob; struct xgene_pmu_dev_ctx *ctx; struct xgene_pmu *xgene_pmu = dev_id; - unsigned long flags; u32 val; - raw_spin_lock_irqsave(&xgene_pmu->lock, flags); + raw_spin_lock(&xgene_pmu->lock); /* Get Interrupt PMU source */ val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG); @@ -1273,7 +1272,7 @@ static irqreturn_t xgene_pmu_isr(int irq, void *dev_id) } } - raw_spin_unlock_irqrestore(&xgene_pmu->lock, flags); + raw_spin_unlock(&xgene_pmu->lock); return IRQ_HANDLED; }