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Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lIAc9-00F7T3-VZ; Fri, 05 Mar 2021 13:35:34 +0000 Received: from inva021.nxp.com ([92.121.34.21]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lIAXe-00F5vM-EJ for linux-arm-kernel@lists.infradead.org; Fri, 05 Mar 2021 13:31:06 +0000 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3634B201495; Fri, 5 Mar 2021 14:30:54 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E832D2010AC; Fri, 5 Mar 2021 14:30:48 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 461D3402A6; Fri, 5 Mar 2021 14:30:43 +0100 (CET) From: Dong Aisheng To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: dongas86@gmail.com, kernel@pengutronix.de, shawnguo@kernel.org, robh+dt@kernel.org, linux-imx@nxp.com, jan.kiszka@siemens.com, Dong Aisheng Subject: [PATCH v5 10/18] arm64: dts: imx8: switch to new lpcg clock binding Date: Fri, 5 Mar 2021 21:17:40 +0800 Message-Id: <1614950268-22073-12-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614950268-22073-1-git-send-email-aisheng.dong@nxp.com> References: <1614950268-22073-1-git-send-email-aisheng.dong@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210305_133054_972785_2894A2AD X-CRM114-Status: GOOD ( 10.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org switch to new lpcg clock binding Signed-off-by: Dong Aisheng --- ChangeLog: v3->5: * no changes except rebase to latest kernel v2->v3: * use new clock-indices IDs v1->v2: * split scu clock changes --- .../boot/dts/freescale/imx8-ss-adma.dtsi | 46 ++++++++++--------- .../boot/dts/freescale/imx8-ss-conn.dtsi | 44 +++++++++--------- .../boot/dts/freescale/imx8-ss-lsio.dtsi | 13 ++++-- .../boot/dts/freescale/imx8qxp-ss-adma.dtsi | 4 -- .../boot/dts/freescale/imx8qxp-ss-conn.dtsi | 4 -- .../boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 4 -- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 + 7 files changed, 56 insertions(+), 60 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi index 30f2089cfdc4..ff0696d80654 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -20,13 +20,8 @@ dma_ipg_clk: clock-dma-ipg { clock-output-names = "dma_ipg_clk"; }; - /* LPCG clocks */ - adma_lpcg: clock-controller@59000000 { - reg = <0x59000000 0x2000000>; - #clock-cells = <1>; - }; - dsp_lpcg: clock-controller@59580000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x59580000 0x10000>; #clock-cells = <1>; clocks = <&dma_ipg_clk>, @@ -41,6 +36,7 @@ dsp_lpcg: clock-controller@59580000 { }; dsp_ram_lpcg: clock-controller@59590000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x59590000 0x10000>; #clock-cells = <1>; clocks = <&dma_ipg_clk>; @@ -52,9 +48,9 @@ dsp_ram_lpcg: clock-controller@59590000 { adma_dsp: dsp@596e8000 { compatible = "fsl,imx8qxp-dsp"; reg = <0x596e8000 0x88000>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; + clocks = <&dsp_lpcg IMX_LPCG_CLK_5>, + <&dsp_ram_lpcg IMX_LPCG_CLK_4>, + <&dsp_lpcg IMX_LPCG_CLK_7>; clock-names = "ipg", "ocram", "core"; power-domains = <&pd IMX_SC_R_MU_13A>, <&pd IMX_SC_R_MU_13B>, @@ -73,8 +69,8 @@ adma_dsp: dsp@596e8000 { adma_lpuart0: serial@5a060000 { reg = <0x5a060000 0x1000>; interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; + clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, + <&uart0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; power-domains = <&pd IMX_SC_R_UART_0>; status = "disabled"; @@ -83,8 +79,8 @@ adma_lpuart0: serial@5a060000 { adma_lpuart1: serial@5a070000 { reg = <0x5a070000 0x1000>; interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; + clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, + <&uart1_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; power-domains = <&pd IMX_SC_R_UART_1>; status = "disabled"; @@ -93,8 +89,8 @@ adma_lpuart1: serial@5a070000 { adma_lpuart2: serial@5a080000 { reg = <0x5a080000 0x1000>; interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; + clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, + <&uart2_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; power-domains = <&pd IMX_SC_R_UART_2>; status = "disabled"; @@ -103,14 +99,15 @@ adma_lpuart2: serial@5a080000 { adma_lpuart3: serial@5a090000 { reg = <0x5a090000 0x1000>; interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; + clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, + <&uart3_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; power-domains = <&pd IMX_SC_R_UART_3>; status = "disabled"; }; uart0_lpcg: clock-controller@5a460000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a460000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, @@ -122,6 +119,7 @@ uart0_lpcg: clock-controller@5a460000 { }; uart1_lpcg: clock-controller@5a470000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a470000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, @@ -133,6 +131,7 @@ uart1_lpcg: clock-controller@5a470000 { }; uart2_lpcg: clock-controller@5a480000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a480000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, @@ -144,6 +143,7 @@ uart2_lpcg: clock-controller@5a480000 { }; uart3_lpcg: clock-controller@5a490000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a490000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, @@ -157,7 +157,7 @@ uart3_lpcg: clock-controller@5a490000 { adma_i2c0: i2c@5a800000 { reg = <0x5a800000 0x4000>; interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; + clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -168,7 +168,7 @@ adma_i2c0: i2c@5a800000 { adma_i2c1: i2c@5a810000 { reg = <0x5a810000 0x4000>; interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; + clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -179,7 +179,7 @@ adma_i2c1: i2c@5a810000 { adma_i2c2: i2c@5a820000 { reg = <0x5a820000 0x4000>; interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; + clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -190,7 +190,7 @@ adma_i2c2: i2c@5a820000 { adma_i2c3: i2c@5a830000 { reg = <0x5a830000 0x4000>; interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; + clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -199,6 +199,7 @@ adma_i2c3: i2c@5a830000 { }; i2c0_lpcg: clock-controller@5ac00000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, @@ -210,6 +211,7 @@ i2c0_lpcg: clock-controller@5ac00000 { }; i2c1_lpcg: clock-controller@5ac10000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac10000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, @@ -221,6 +223,7 @@ i2c1_lpcg: clock-controller@5ac10000 { }; i2c2_lpcg: clock-controller@5ac20000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac20000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, @@ -232,6 +235,7 @@ i2c2_lpcg: clock-controller@5ac20000 { }; i2c3_lpcg: clock-controller@5ac30000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac30000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 83945cc720e1..1ce40a1a092e 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -37,9 +37,9 @@ conn_ipg_clk: clock-conn-ipg { usdhc1: mmc@5b010000 { interrupts = ; reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; + clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, + <&sdhc0_lpcg IMX_LPCG_CLK_0>, + <&sdhc0_lpcg IMX_LPCG_CLK_5>; clock-names = "ipg", "per", "ahb"; power-domains = <&pd IMX_SC_R_SDHC_0>; status = "disabled"; @@ -48,9 +48,9 @@ usdhc1: mmc@5b010000 { usdhc2: mmc@5b020000 { interrupts = ; reg = <0x5b020000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; + clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, + <&sdhc1_lpcg IMX_LPCG_CLK_0>, + <&sdhc1_lpcg IMX_LPCG_CLK_5>; clock-names = "ipg", "per", "ahb"; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; @@ -61,9 +61,9 @@ usdhc2: mmc@5b020000 { usdhc3: mmc@5b030000 { interrupts = ; reg = <0x5b030000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; + clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, + <&sdhc2_lpcg IMX_LPCG_CLK_0>, + <&sdhc2_lpcg IMX_LPCG_CLK_5>; clock-names = "ipg", "per", "ahb"; power-domains = <&pd IMX_SC_R_SDHC_2>; status = "disabled"; @@ -75,10 +75,10 @@ fec1: ethernet@5b040000 { , , ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; + clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, + <&enet0_lpcg IMX_LPCG_CLK_2>, + <&enet0_lpcg IMX_LPCG_CLK_1>, + <&enet0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; @@ -92,10 +92,10 @@ fec2: ethernet@5b050000 { , , ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; + clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, + <&enet1_lpcg IMX_LPCG_CLK_2>, + <&enet1_lpcg IMX_LPCG_CLK_1>, + <&enet1_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; @@ -104,12 +104,8 @@ fec2: ethernet@5b050000 { }; /* LPCG clocks */ - conn_lpcg: clock-controller-legacy@5b200000 { - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; - }; - sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b200000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, @@ -123,6 +119,7 @@ sdhc0_lpcg: clock-controller@5b200000 { }; sdhc1_lpcg: clock-controller@5b210000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b210000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, @@ -136,6 +133,7 @@ sdhc1_lpcg: clock-controller@5b210000 { }; sdhc2_lpcg: clock-controller@5b220000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b220000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, @@ -149,6 +147,7 @@ sdhc2_lpcg: clock-controller@5b220000 { }; enet0_lpcg: clock-controller@5b230000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b230000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, @@ -166,6 +165,7 @@ enet0_lpcg: clock-controller@5b230000 { }; enet1_lpcg: clock-controller@5b240000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b240000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 813dbac71d10..ee4e585a9c39 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -149,12 +149,8 @@ lsio_mu13: mailbox@5d280000 { }; /* LPCG clocks */ - lsio_lpcg: clock-controller-legacy@5d400000 { - reg = <0x5d400000 0x400000>; - #clock-cells = <1>; - }; - pwm0_lpcg: clock-controller@5d400000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d400000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, @@ -174,6 +170,7 @@ pwm0_lpcg: clock-controller@5d400000 { }; pwm1_lpcg: clock-controller@5d410000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d410000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, @@ -193,6 +190,7 @@ pwm1_lpcg: clock-controller@5d410000 { }; pwm2_lpcg: clock-controller@5d420000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d420000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, @@ -212,6 +210,7 @@ pwm2_lpcg: clock-controller@5d420000 { }; pwm3_lpcg: clock-controller@5d430000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d430000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, @@ -231,6 +230,7 @@ pwm3_lpcg: clock-controller@5d430000 { }; pwm4_lpcg: clock-controller@5d440000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d440000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, @@ -250,6 +250,7 @@ pwm4_lpcg: clock-controller@5d440000 { }; pwm5_lpcg: clock-controller@5d450000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d450000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, @@ -269,6 +270,7 @@ pwm5_lpcg: clock-controller@5d450000 { }; pwm6_lpcg: clock-controller@5d460000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d460000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, @@ -288,6 +290,7 @@ pwm6_lpcg: clock-controller@5d460000 { }; pwm7_lpcg: clock-controller@5d470000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d470000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi index 64e51dda2dfd..3dc3238e7ca6 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -4,10 +4,6 @@ * Dong Aisheng */ -&adma_lpcg { - compatible = "fsl,imx8qxp-lpcg-adma"; -}; - &adma_lpuart0 { compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi index bed3934ca029..f5f58959f65c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi @@ -4,10 +4,6 @@ * Dong Aisheng */ -&conn_lpcg { - compatible = "fsl,imx8qxp-lpcg-conn"; -}; - &usdhc1 { compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi index 82cebf04fca9..11395479ffc0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -59,7 +59,3 @@ &lsio_mu4 { &lsio_mu13 { compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; }; - -&lsio_lpcg { - compatible = "fsl,imx8qxp-lpcg-lsio"; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 095d3f69a9b7..9513bb7b5c89 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include #include