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Tue, 06 Apr 2021 20:38:58 -0700 Received: from MTKMBS06N2.mediatek.inc (172.21.101.130) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Apr 2021 20:28:56 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 7 Apr 2021 11:28:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 7 Apr 2021 11:28:53 +0800 From: Flora Fu To: Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd , Liam Girdwood , "Mark Brown" CC: Flora Fu , Pi-Cheng Chen , Chiawen Lee , Chun-Jie Chen , , , , , Subject: [PATCH 5/8] dt-bindings: soc: mediatek: apusys: Add new document for APU power domain Date: Wed, 7 Apr 2021 11:28:03 +0800 Message-ID: <1617766086-5502-6-git-send-email-flora.fu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1617766086-5502-1-git-send-email-flora.fu@mediatek.com> References: <1617766086-5502-1-git-send-email-flora.fu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 42B2CA7540249A853B4F08125BFC10E92DB4B6618A5B217123DDF2CF1714566A2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210407_043918_601979_EB0F889F X-CRM114-Status: GOOD ( 14.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the bindings for APU power domain on MediaTek SoC. Signed-off-by: Flora Fu --- .../soc/mediatek/mediatek,apu-pm.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml new file mode 100644 index 000000000000..c99e812977f9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,apu-pm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek APU Power Domains + +maintainers: + - Flora Fu + +description: | + Mediatek AI Process Unit (APU) include support for power domains which can be + powered up/down by software. + APU subsys belonging to a power domain should contain a 'power-domains' + property that is a phandle for apuspm node representing the domain. + +properties: + compatible: + items: + - enum: + - mediatek,mt8192-apu-pm + - const: syscon + + reg: + description: Address range of the APU power domain controller. + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#power-domain-cells': + const: 1 + + vsram-supply: + description: apu sram regulator supply. + + mediatek,scpsys: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to the device containing the scpsys register range. + + mediatek,apu_conn: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to the device containing the scpsys apu conn register range. + + mediatek,apu_conn1: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to the device containing the scpsys apu conn1 register range. + + mediatek,apu_vcore: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to the device containing the scpsys apu vcore register range. + +patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents the power domains within the power controller node as + documented in Documentation/devicetree/bindings/power/power-domain.yaml. + + properties: + reg: + description: | + Power domain index. Valid values are defined in: + "include/dt-bindings/power/mt8182-apu-power.h" + maxItems: 1 + + '#power-domain-cells': + description: | + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM. + + clocks: + description: | + List of phandles of clocks list. Specify by order according to + power-up sequence. + + clock-names: + description: | + List of names of clocks. Specify by order according to power-up + sequence. + + assigned-clocks: + maxItems: 2 + + assigned-clock-parents: + maxItems: 2 + + domain-supply: + description: domain regulator supply. + + required: + - reg + - '#power-domain-cells' + + additionalProperties: false + +required: + - compatible + - reg + - '#power-domain-cells' + - vsram-supply + - mediatek,scpsys + +additionalProperties: false + +examples: + - | + #include + #include + apuspm: power-domain@190f0000 { + compatible = "mediatek,mt8192-apu-pm", "syscon"; + reg = <0x190f0000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + vsram-supply = <&mt6359_vsram_md_ldo_reg>; + mediatek,scpsys = <&scpsys>; + mediatek,apu_conn = <&apu_conn>; + mediatek,apu_vcore = <&apu_vcore>; + + power-domain@MT8192_POWER_DOMAIN_APUSYS_TOP { + reg = ; + #power-domain-cells = <0>; + clocks = <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_IPU_IF_SEL>, + <&clk26m>, + <&topckgen CLK_TOP_UNIVPLL_D6_D2>; + clock-names = "clk_top_conn", + "clk_top_ipu_if", + "clk_off", + "clk_on_default"; + assigned-clocks = <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_IPU_IF_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_UNIVPLL_D6_D2>; + domain-supply = <&mt6359_vproc1_buck_reg>; + }; + };