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[”PATCH”,5/5] PCI: armada8k: add device reset to link-down handle

Message ID 1618241456-27200-6-git-send-email-bpeled@marvell.com (mailing list archive)
State New
Headers show
Series Asynchronous linkdown recovery | expand

Commit Message

Ben Peled April 12, 2021, 3:30 p.m. UTC
From: Ben Peled <bpeled@marvell.com>

Added pcie reset via gpio support as described in the
designware-pcie.txt DT binding document.
In cases link down cause still exist in device.
The device need to be reset to reestablish the link.
If reset-gpio pin provided in the device tree, then the linkdown
handle resets the device before reestablishing link.

Signed-off-by: Ben Peled <bpeled@marvell.com>
 drivers/pci/controller/dwc/pcie-armada8k.c | 2 ++
 1 file changed, 2 insertions(+)
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diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c
index 4eb8607..83ac91e 100644
--- a/drivers/pci/controller/dwc/pcie-armada8k.c
+++ b/drivers/pci/controller/dwc/pcie-armada8k.c
@@ -24,6 +24,7 @@ 
 #include <linux/of_irq.h>
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
+#include <linux/of_gpio.h>
 #include "pcie-designware.h"
@@ -38,6 +39,7 @@  struct armada8k_pcie {
 	struct regmap *sysctrl_base;
 	u32 mac_rest_bitmask;
 	struct work_struct recover_link_work;
+	enum of_gpio_flags flags;
 #define PCIE_VENDOR_REGS_OFFSET		0x8000