| Message ID | 1618367174-30968-2-git-send-email-hongxing.zhu@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mq-evk: add one regulator used to power up pcie phy | expand |
Hi Shawn: Regarding Lucas' advice, this patch should be split out and post for you to pick up into DT tree. Since the other two patches are accepted by PCIe tree now. Can you help to pick up this patch? Thanks in advanced. https://patchwork.kernel.org/project/linux-pci/patch/1616661882-26487-3-git-send-email-hongxing.zhu@nxp.com/ https://patchwork.kernel.org/project/linux-pci/patch/1617091701-6444-2-git-send-email-hongxing.zhu@nxp.com/ Best Regards Richard Zhu > -----Original Message----- > From: Richard Zhu <hongxing.zhu@nxp.com> > Sent: Wednesday, April 14, 2021 10:26 AM > To: shawnguo@kernel.org > Cc: l.stach@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Richard > Zhu <hongxing.zhu@nxp.com> > Subject: [PATCH] arm64: dts: imx8mq-evk: add one regulator used to power > up pcie phy > > Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY. > In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data sheet. > When PCIE_VPH is supplied by 3.3v in the HW schematic design, the > VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1 > to 1b'0. Thus, the internal 3v3 to 1v8 translator would be turned on. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > index 85b045253a0e..4d2035e3dd7c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > @@ -318,6 +318,7 @@ > <&clk IMX8MQ_CLK_PCIE1_PHY>, > <&pcie0_refclk>; > clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; > + vph-supply = <&vgen5_reg>; > status = "okay"; > }; > > -- > 2.17.1
On Wed, Apr 14, 2021 at 10:26:14AM +0800, Richard Zhu wrote: > Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY. > In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data > sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, > the VREG_BYPASS bits of GPR registers should be cleared from default > value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be > turned on. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Applied, thanks.
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 85b045253a0e..4d2035e3dd7c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -318,6 +318,7 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + vph-supply = <&vgen5_reg>; status = "okay"; };