| Message ID | 1622616875-22740-1-git-send-email-u0084500@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] regulator: mt6360: Add optional mediatek.power-off-sequence in bindings document | expand |
On Wed, Jun 02, 2021 at 02:54:34PM +0800, cy_huang wrote: > From: ChiYuan Huang <cy_huang@richtek.com> > > Add optional mediatek.power-off-sequence in bindings document. > > Signed-off-by: ChiYuan Huang <cy_huang@richtek.com> > --- > Hi, > > Originally, we think it must write in platform dependent code like as bootloader. > But after the evaluation, it must write only when system normal HALT or POWER_OFF. > For the other cases, just follow HW immediate off by default. Wouldn't this be handled by PSCI implementation? > --- > .../devicetree/bindings/regulator/mt6360-regulator.yaml | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml > index a462d99..eaf36e2 100644 > --- a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml > +++ b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml > @@ -24,6 +24,16 @@ properties: > LDO_VIN3-supply: > description: Input supply phandle(s) for LDO6/7 > > + mediatek,power-off-sequence: > + description: | > + Power off sequence time selection for BUCK1/BUCK2/LDO7/LDO6, respetively. > + Cause these regulators are all default-on power. Each value from 0 to 63, > + and step is 1. Each step means 2 millisecond delay. > + Therefore, the power off sequence delay time range is from 0ms to 126ms. > + $ref: "/schemas/types.yaml#/definitions/uint8-array" > + minItems: 4 > + maxItems: 4 So this is the delay between BUCK1 and BUCK2, then BUCK2 to LDO7, etcc? If we wanted to express this in DT, we'd made this generic which would need to be more flexible. A poweroff delay in each regulator (similar to the existing power on delay) would be sufficient for what you need I think. Rob
Hi, Rob: Rob Herring <robh@kernel.org> 於 2021年6月12日 週六 上午4:16寫道： > > On Wed, Jun 02, 2021 at 02:54:34PM +0800, cy_huang wrote: > > From: ChiYuan Huang <cy_huang@richtek.com> > > > > Add optional mediatek.power-off-sequence in bindings document. > > > > Signed-off-by: ChiYuan Huang <cy_huang@richtek.com> > > --- > > Hi, > > > > Originally, we think it must write in platform dependent code like as bootloader. > > But after the evaluation, it must write only when system normal HALT or POWER_OFF. > > For the other cases, just follow HW immediate off by default. > > Wouldn't this be handled by PSCI implementation? No, the current application default on powers buck1/buck2/ldo7/ldo6 are for Dram power. It's not the soc core power. It seems not appropriate to implement like as PSCI. MT6360 play the role for the subpmic in the SOC application reference design. > > > --- > > .../devicetree/bindings/regulator/mt6360-regulator.yaml | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml > > index a462d99..eaf36e2 100644 > > --- a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml > > +++ b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml > > @@ -24,6 +24,16 @@ properties: > > LDO_VIN3-supply: > > description: Input supply phandle(s) for LDO6/7 > > > > + mediatek,power-off-sequence: > > + description: | > > + Power off sequence time selection for BUCK1/BUCK2/LDO7/LDO6, respetively. > > + Cause these regulators are all default-on power. Each value from 0 to 63, > > + and step is 1. Each step means 2 millisecond delay. > > + Therefore, the power off sequence delay time range is from 0ms to 126ms. > > + $ref: "/schemas/types.yaml#/definitions/uint8-array" > > + minItems: 4 > > + maxItems: 4 > > So this is the delay between BUCK1 and BUCK2, then BUCK2 to LDO7, etcc? No. you may misunderstand. there's an external 'Enable' pin that's connected to the main pmic. The starting point of delay time are all from the external 'Enable' H to L. Not one-by-one delay time, > If we wanted to express this in DT, we'd made this generic which would > need to be more flexible. A poweroff delay in each regulator (similar to > the existing power on delay) would be sufficient for what you need I > think. Power on sequence already defined by the part number, It's not decided by SW. So for the flexibility, I implement it in DT. Duel to there're many part number MT6360 P/UP/LP, etc. The difference are the power on sequence. Do you have any suggestion about this situation? PS: Due to DRAM power usage , sometimes it also need to customized by the DRAM that customer choosed. It may differ from external DRAM part choosen following by JEDEC spec. > > Rob
On Fri, Jun 11, 2021 at 02:16:43PM -0600, Rob Herring wrote: > On Wed, Jun 02, 2021 at 02:54:34PM +0800, cy_huang wrote: > > Originally, we think it must write in platform dependent code like as bootloader. > > But after the evaluation, it must write only when system normal HALT or POWER_OFF. > > For the other cases, just follow HW immediate off by default. > Wouldn't this be handled by PSCI implementation? Ideally I think... > > + mediatek,power-off-sequence: > > + description: | > > + Power off sequence time selection for BUCK1/BUCK2/LDO7/LDO6, respetively. > > + Cause these regulators are all default-on power. Each value from 0 to 63, > > + and step is 1. Each step means 2 millisecond delay. > > + Therefore, the power off sequence delay time range is from 0ms to 126ms. > > + $ref: "/schemas/types.yaml#/definitions/uint8-array" > > + minItems: 4 > > + maxItems: 4 > So this is the delay between BUCK1 and BUCK2, then BUCK2 to LDO7, etcc? > If we wanted to express this in DT, we'd made this generic which would > need to be more flexible. A poweroff delay in each regulator (similar to > the existing power on delay) would be sufficient for what you need I > think. It's not exactly a delay that's being described there - it's a series of timeslots, each regulator getting assigned to a timeslot. You could possibly do a general binding by specifying a delay from the start of the power off sequence and then (for this device) having the driver work out a mapping of those times to timeslots. That feels genericish, you might also have things like mode changes but it'd cover a lot of the cases. On the other hand this is the sort of thing that is often just not configurable and where people often make weird and inflexible hardware so things that do implement it are likely to end up wanting to add a bunch of constraints which might be a lot of hassle.
On Mon, Jun 14, 2021 at 11:04:01PM +0800, ChiYuan Huang wrote: > Rob Herring <robh@kernel.org> 於 2021年6月12日 週六 上午4:16寫道： > > > Originally, we think it must write in platform dependent code like as bootloader. > > > But after the evaluation, it must write only when system normal HALT or POWER_OFF. > > > For the other cases, just follow HW immediate off by default. > > Wouldn't this be handled by PSCI implementation? > No, the current application default on powers buck1/buck2/ldo7/ldo6 > are for Dram power. > It's not the soc core power. It seems not appropriate to implement > like as PSCI. > MT6360 play the role for the subpmic in the SOC application reference design. If this is part of the overall system power off that seems like it fits well enough into what PSCI is doing - it's got operations like SYSTEM_OFF which talk about the system as a whole.
Mark Brown <broonie@kernel.org> 於 2021年6月18日 週五 上午12:29寫道： > > On Mon, Jun 14, 2021 at 11:04:01PM +0800, ChiYuan Huang wrote: > > Rob Herring <robh@kernel.org> 於 2021年6月12日 週六 上午4:16寫道： > > > > > Originally, we think it must write in platform dependent code like as bootloader. > > > > But after the evaluation, it must write only when system normal HALT or POWER_OFF. > > > > For the other cases, just follow HW immediate off by default. > > > > Wouldn't this be handled by PSCI implementation? > > > No, the current application default on powers buck1/buck2/ldo7/ldo6 > > are for Dram power. > > It's not the soc core power. It seems not appropriate to implement > > like as PSCI. > > MT6360 play the role for the subpmic in the SOC application reference design. > > If this is part of the overall system power off that seems like it fits > well enough into what PSCI is doing - it's got operations like > SYSTEM_OFF which talk about the system as a whole. Thanks, I'll check and survey the PSCI about the SYSTEM_OFF. I think it may work.
diff --git a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml index a462d99..eaf36e2 100644 --- a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml @@ -24,6 +24,16 @@ properties: LDO_VIN3-supply: description: Input supply phandle(s) for LDO6/7 + mediatek,power-off-sequence: + description: | + Power off sequence time selection for BUCK1/BUCK2/LDO7/LDO6, respetively. + Cause these regulators are all default-on power. Each value from 0 to 63, + and step is 1. Each step means 2 millisecond delay. + Therefore, the power off sequence delay time range is from 0ms to 126ms. + $ref: "/schemas/types.yaml#/definitions/uint8-array" + minItems: 4 + maxItems: 4 + patternProperties: "^buck[12]$": $ref: "regulator.yaml#" @@ -42,6 +52,7 @@ examples: #include <dt-bindings/regulator/mediatek,mt6360-regulator.h> regulator { compatible = "mediatek,mt6360-regulator"; + mediatek,power-off-sequence = /bits/ 8 <0 0 0 0>; LDO_VIN3-supply = <&BUCK2>; buck1 { regulator-compatible = "BUCK1";