From patchwork Mon Aug 2 04:42:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 12413269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA1FBC4338F for ; Mon, 2 Aug 2021 04:44:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A43060FC1 for ; Mon, 2 Aug 2021 04:44:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9A43060FC1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=61241w7rV05W0c+bMktVP0ZC7g4SaebrKbcAOh6WHrU=; b=C7POVXRDJnlXyz Se3FESSlO/iZ9m9JLNadPK2LEPA08gaRWsLrZzzw0nqi0fnwPRvfEQNCwRqFSv3CTTir/eWSz9Hg1 UApUxjPjQpxt+8TeTEFDg58Lo4dCCqBB8zeYbmTostumsNDO1yTjE+rhdLtP362pBIhFgskx1pw/v ASrFKy46TAz9DJMwCObcvyJTckLvWTHQlJPy16RPlQ4yNGdIa58rRAwy4PYqrptch7UgYcXCifIO5 BswI4eV3hPZf933/qoOSmCk7opiBJaaDndhFXv5kYe/IXJ4SmjP1f4u2LTnPqnhSJNoITlbvpajkQ jEeIZjzt+d2K43J0bQYw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mAPmE-00ExGY-2U; Mon, 02 Aug 2021 04:42:10 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mAPm9-00ExFs-LW for linux-arm-kernel@lists.infradead.org; Mon, 02 Aug 2021 04:42:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2A583106F; Sun, 1 Aug 2021 21:42:00 -0700 (PDT) Received: from p8cg001049571a15.arm.com (unknown [10.163.66.153]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 072643F70D; Sun, 1 Aug 2021 21:41:56 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , James Morse , Marc Zyngier , Mark Rutland , linux-kernel@vger.kernel.org Subject: [PATCH] arm64/mm: Fix idmap on [16K|36VA|48PA] Date: Mon, 2 Aug 2021 10:12:39 +0530 Message-Id: <1627879359-30303-1-git-send-email-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210801_214205_798216_5B995212 X-CRM114-Status: GOOD ( 12.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When creating the idmap, the kernel may add one extra level to idmap memory outside the VA range. But for [16K|36VA|48PA], we need two levels to reach 48 bits. If the bootloader places the kernel in memory above (1 << 46), the kernel will fail to enable the MMU. Although we are not aware of a platform where this happens, it is worth to accommodate such scenarios and prevent a possible kernel crash. Lets fix the problem on the above configuration by creating two additional idmap page table levels when 'idmap_text_end' is outside the VA range. This reduces 'idmap_t0sz' to cover the entire PA range which would prevent table misconfiguration (fault) when a given 'idmap_t0sz' value requires a single additional page table level where as two have been built. Cc: Catalin Marinas Cc: Will Deacon Cc: James Morse Cc: Marc Zyngier Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Fixes: 215399392fe4 ("arm64: 36 bit VA") Signed-off-by: Anshuman Khandual --- This applies on v5.14-rc4 RFC: https://lore.kernel.org/lkml/1627019894-14819-1-git-send-email-anshuman.khandual@arm.com/ arch/arm64/kernel/head.S | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index c5c994a..da33bbc 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -329,7 +329,9 @@ SYM_FUNC_START_LOCAL(__create_page_tables) #if (VA_BITS < 48) #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) +#define EXTRA_SHIFT_1 (EXTRA_SHIFT + PAGE_SHIFT - 3) #define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT)) +#define EXTRA_PTRS_1 (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT_1)) /* * If VA_BITS < 48, we have to configure an additional table level. @@ -342,8 +344,30 @@ SYM_FUNC_START_LOCAL(__create_page_tables) #error "Mismatch between VA_BITS and page size/number of translation levels" #endif +/* + * In this particular CONFIG_ARM64_16K_PAGES config, there might be a + * scenario where 'idmap_text_end' ends up high enough in the PA range + * requiring two additional idmap page table levels. Reduce idmap_t0sz + * to cover the entire PA range. This prevents table misconfiguration + * when a given idmap_t0sz value just requires single additional level + * where as two levels have been built. + */ +#if defined(CONFIG_ARM64_VA_BITS_36) && defined(CONFIG_ARM64_PA_BITS_48) + mov x4, EXTRA_PTRS_1 + create_table_entry x0, x3, EXTRA_SHIFT_1, x4, x5, x6 + + mov x4, PTRS_PER_PTE + create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6 + + mov x5, #64 - PHYS_MASK_SHIFT + adr_l x6, idmap_t0sz + str x5, [x6] + dmb sy + dc ivac, x6 +#else mov x4, EXTRA_PTRS create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6 +#endif #else /* * If VA_BITS == 48, we don't have to configure an additional