From patchwork Tue Jul 5 09:11:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bough Chen X-Patchwork-Id: 12906146 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36718C433EF for ; Tue, 5 Jul 2022 09:28:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UlPfyFg5cuqj0Tt0ouEoR1pPgY4tTeUrk7jrvfbRha4=; b=yxv1vVcB3QzJL3 6nxR/b1Pz4e50dFgY80EbtVlk5eEP/CxYoxxy6xWu1q8NaEyxhskS7orzgYI/opShDwnBF0MCNkBN 4XpFdaQpMIx8RmPwWkO/3ZITGgvnY5lKXjhm3Ag0ngaE8T/YJS7SXslcilJu0Vovp2Y7weMi6B6XN Ia8EuVkFECGT4g/mQTVqsR5OIF2tk31CB6Q0HZlRtTAJLqVJPWyeqgo9YpeS3UQGwUG/Smrc2n9HP 6+tjhyKC5tfepgpZyNR+r1z7XKep9rU/n32JCnyBBBeC9d/9oB+1gIfF9pVAFLLlvZ6/mjNBaW5sQ 2XC9hb8BIrMKuCAKsNeQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8eq3-00GghW-1s; Tue, 05 Jul 2022 09:27:23 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8epc-00GgSf-MB; Tue, 05 Jul 2022 09:26:58 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C87411A0AD0; Tue, 5 Jul 2022 11:26:52 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 65F9C1A0AE0; Tue, 5 Jul 2022 11:26:52 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 059DE181D0CA; Tue, 5 Jul 2022 17:26:49 +0800 (+08) From: haibo.chen@nxp.com To: ashish.kumar@nxp.com, yogeshgaur.83@gmail.com, broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, han.xu@nxp.com, singh.kuldeep87k@gmail.com, tudor.ambarus@microchip.com, p.yadav@ti.com, michael@walle.cc, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, festevam@gmail.com, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, haibo.chen@nxp.com, zhengxunli@mxic.com.tw Subject: [PATCH 04/11] spi: spi-nxp-fspi: add function to select sample clock source for flash reading Date: Tue, 5 Jul 2022 17:11:36 +0800 Message-Id: <1657012303-6464-4-git-send-email-haibo.chen@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1657012303-6464-1-git-send-email-haibo.chen@nxp.com> References: <1657012303-6464-1-git-send-email-haibo.chen@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220705_022657_038026_444476E8 X-CRM114-Status: GOOD ( 11.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Haibo Chen fspi define four mode for sample clock source selection. Here is the list of modes: mode 0: Dummy Read strobe generated by FlexSPI Controller and loopback internally mode 1: Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad mode 2: Reserved mode 3: Flash provided Read strobe and input from DQS pad In default, fspi use mode 0 after reset. For 8-8-8-DTR mode, need to use mode 3, otherwise 8-8-8-DTR read always get incorrect data. Signed-off-by: Haibo Chen --- drivers/spi/spi-nxp-fspi.c | 47 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index c32a4f53fa2a..34679dc0e1ad 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -380,6 +380,7 @@ struct nxp_fspi { struct pm_qos_request pm_qos_req; int selected; #define FSPI_INITILIZED (1 << 0) +#define FSPI_RXCLKSRC_3 (1 << 1) int flags; }; @@ -877,6 +878,50 @@ static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) return err; } +/* + * Sample Clock source selection for Flash Reading + * Four modes defined by fspi: + * mode 0: Dummy Read strobe generated by FlexSPI Controller + * and loopback internally + * mode 1: Dummy Read strobe generated by FlexSPI Controller + * and loopback from DQS pad + * mode 2: Reserved + * mode 3: Flash provided Read strobe and input from DQS pad + * + * fspi default use mode 0 after reset + */ +static void nxp_fspi_select_rx_sample_clk_source(struct nxp_fspi *f, + const struct spi_mem_op *op) +{ + u32 reg; + + /* + * For 8-8-8-DTR mode, need to use mode 3 (Flash provided Read + * strobe and input from DQS pad), otherwise read operaton may + * meet issue. + * This mode require flash device connect the DQS pad on board. + * For other modes, still use mode 0, keep align with before. + * spi_nor_suspend will disable 8-8-8-DTR mode, also need to + * change the mode back to mode 0. + */ + if (!(f->flags & FSPI_RXCLKSRC_3) && + op->cmd.dtr && op->addr.dtr && + op->dummy.dtr && op->data.dtr) { + reg = fspi_readl(f, f->iobase + FSPI_MCR0); + reg |= FSPI_MCR0_RXCLKSRC(3); + fspi_writel(f, reg, f->iobase + FSPI_MCR0); + f->flags |= FSPI_RXCLKSRC_3; + } else if ((f->flags & FSPI_RXCLKSRC_3) && + !op->cmd.dtr && !op->addr.dtr && + !op->dummy.dtr && !op->data.dtr) { + reg = fspi_readl(f, f->iobase + FSPI_MCR0); + reg &= ~FSPI_MCR0_RXCLKSRC(3); /* select mode 0 */ + fspi_writel(f, reg, f->iobase + FSPI_MCR0); + f->flags &= ~FSPI_RXCLKSRC_3; + } + +} + static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); @@ -897,6 +942,8 @@ static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) nxp_fspi_select_mem(f, mem->spi); + nxp_fspi_select_rx_sample_clk_source(f, op); + nxp_fspi_prepare_lut(f, op); /* * If we have large chunks of data, we read them through the AHB bus by